Applied Materials, Inc.

National Semiconductor Corporation

Other

Novellus Systems Incorporated

Jen Shu

Michael E Thomas

Christopher Dennis Bencher

Patrick A Van Cleemput

Lisong Zhou

Ravi Kumar Laxman

Bunsen B Nie

Michael P Stewart

Michelle T Schulberg

Li (Sherry) Xu

Li-Qun Xia

Ellie Y Yieh

Suketu Arun Parikh

Huixiong Dai

Hui W Chen

Frederic Gaillard

Bencherki Mebarki

Raymond Hoiman Hung

James M Gee

Michael Duane

Yongmei Chen

Tian-Hoe Lim

Li Yan Miao

Chorng-Ping Chang

Christopher Siu Wing Ngai

Susie Xiuru Yang

Xumou Xu

Kenneth MacWilliams

Jiahua Yu

Prochy Sethna

A fabrication line includes a texturizing module configured to texture a substrate, an emitter module configured to form an emitter region, a passivation layer module configured to form a passivation layer, a barrier contact module configured to form a barrier contact region, a firing module configured to anneal the barrier contact region, a top metal contact module configured to form a top metal contact region, and a soldering module configured to solder the barrier contact region to the top metal contact region. The modules are integrated by one or more automated substrate handlers into a single fabrication line. A method for fabricating a solar cell includes sequentially, in an automated fabrication line: doping a dopant in a substrate; disposing a passivation layer; disposing and annealing a barrier metal paste to form a barrier contact; and disposing and annealing a metal contact paste to form a top metal contact region.

Contact and interconnect metallization for solar cells

Methods to pattern features in a substrate layer by exposing a photoresist layer more than once. In one embodiment, a single reticle may be exposed more than once with an overlay offset implemented between successive exposures to reduce the half pitch of the reticle. In particular embodiments, these methods may be employed to reduce the half pitch of the features printed with 65 nm generation lithography equipment to achieve 45 nm lithography generation CD and pitch performance.

Double exposure patterning with carbonaceous hardmask

The present invention generally provides a method of forming a high efficiency solar cell device by preparing a surface and/or forming at least a part of a high quality passivation layer on a silicon containing substrate. Embodiments of the present invention may be especially useful for preparing a surface of a p-type doped region formed on a silicon substrate so that a high quality passivation layer can be formed thereon. In one embodiment, the methods include exposing a surface of the solar cell substrate to a plasma to clean and modify the physical, chemical and/or electrical characteristics of the surface.

Method of cleaning and forming a negatively charged passivation layer over a doped region

Embodiments of the present invention pertain to methods of forming patterned features on a substrate having a reduced pitch in two dimensions as compared to what is possible using standard photolithography processing techniques using a single high-resolution photomask. A spacer layer is formed over a two-dimensional square grid of cores with a thickness chosen to leave a dimple at the center of four cores on the corners of a square. The spacer layer is etched back to reveal the substrate at the centers of the square. Removing the core material results in double the pattern density of the lithographically defined grid of cores. The regions of exposed substrate may be filled again with core material and the process repeated to quadruple the pattern density.

Self-aligned multi-patterning for advanced critical dimension contacts

An embodiment of the present invention provides methods for forming a carbon-containing layer having a low dielectric constant and good gap-fill capabilities. A method includes depositing a carbon-containing layer on a substrate and transforming the carbon-containing layer to remove at least some of the carbon. The transforming step may include annealing the carbon-containing layer in a furnace containing a hydrogen atmosphere, for example. The carbon-containing layer may be a carbon-doped silicon oxide material, where the transforming step changes the carbon-doped silicon oxide. Additionally, the method may include subjecting the annealed layer to a hydrogen and/or low oxygen plasma treatment to further remove carbon from the layer. Additionally, a step of adding a capping layer to the annealed, plasma treated material is provided. Products made by the above methods are also included, such as a product including a low k carbon-containing layer where the low k carbon-containing layer has been transformed to remove some of the carbon from the layer. An additional product includes a transformed carbon-containing layer further subjected to a hydrogen plasma treatment to remove more carbon from the layer. Further, a capping layer deposited over the transformed and hydrogen plasma treated layer is provided.

Process for forming a low dielectric constant carbon-containing film

Substrate bombardment during HDP deposition of carbon-doped silicon oxide film results in filling the gaps between metal lines with carbon-doped low k dielectric material. This leads to the placement of low k dielectric between the narrow metal lines while the films over the metal lines have higher dielectric constant due to removal of carbon from these films during ion bombardment. Films over the metal lines have properties similar to silicon dioxide and are ready for sequential integration processes.

Dielectric gap fill process that effectively reduces capacitance between narrow metal lines using HDP-CVD

Thin films possessing low dielectric constants (e.g., dielectric constants below 3.0) are formed on integrated circuits or other substrates. Caged-siloxane precursors are linked in such a way as to form dielectric layers, which exhibit low dielectric constants by virtue of their silicon dioxide-like molecular structure and porous nature. Supercritical fluids may be used as the reaction medium and developer both to the dissolve and deliver the caged-siloxane precursors and to remove reagents and byproducts from the reaction chamber and resultant porous film created.

Dielectric films with low dielectric constants

A planarization process in which an organic film prevents oxide dishing during the chemical mechanical polishing step. In the planarization process an organic film having high CMP selectivity to silicon dioxide is spun over silicon dioxide. A patterned mask is then placed over the organic film and the exposed portions of the organic film are etched away. The remaining portions of the organic film prevent oxide dishing during chemical mechanical polishing because the high CMP selectivity of the organic film to silicon dioxide stops the etching before oxide dishing occurs. The organic film may then be oxygen ashed off the planarized surface if so desired.

Method of using organic material to enhance STI planarization or other planarization processes

A chemical vapor deposition (CVD) process uses a precursor gas, such as with a siloxane or alkylsilane, and a carbon-dioxide-containing gas, such as CO with O or CO with C H OH where 1&lE;x&lE;5, to deposit a dielectric layer with no photoresist &ldquo;footing&rdquo;, a low dielectric constant, and high degrees of adhesion and hardness. Because nitrogen is not used in the deposition process (the carbon-dioxide-containing gas replaces nitrogen-containing gases in conventional processes), amines do not build into the deposited layer, thereby preventing photoresist &ldquo;footing&rdquo;.

Method to deposit SiOCH films with dielectric constant below 3.0

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Saratoga, CA, United States of America

Jen Shu