Nan Ya Technology Corporation

Jen-Jui Huang

Kuo-Yao Cho

Shing-Yih Shih

Shian-Jyh Lin

Chiang-Lin Shih

Jeng-Ping Lin

Wen-Bin Wu

Hsiu-Chun Lee

Chin-Piao Chang

Hung-Ming Tsai

Chang-Ho Yeh

Yu-Chung Fang

Hong-Wen Lee

Kuo-Chung Chen

Jing-Kae Liou

A method of forming dense hole patterns of semiconductor devices includes: forming a plurality of first pillars on at least one lower hard mask layer disposed on a substrate; forming a spacer layer on the lower hard mask layer to form a plurality of second pillars respectively covering the first pillars, wherein a plurality of first holes are formed among the second pillars; etching the spacer layer to expose first portions of the lower hard mask layer via the first holes and expose top surfaces of the first pillars; removing the first pillars to form a plurality of second holes in the spacer layer to expose second portions of the lower hard mask layer; etching the first portions and the second portions of the lower hard mask layer at least until portions of the substrate are exposed; and removing remaining portions of the spacer layer.

Method of forming dense hole patterns of semiconductor devices

A method of manufacturing a semiconductor structure. A patterned first hard mask is formed on a substrate. The patterned first hard mask includes first trench patterns extending along a first direction. A second hard mask is then formed on the patterned first hard mask. A patterned photoresist layer is formed on the second hard mask. The patterned photoresist layer includes second trench patterns extending along a second direction. The second trench patterns intersect first trench patterns. Using the patterned photoresist layer as an etch mask, a first etch process is performed to transfer the second trench patterns into the patterned first hard mask and the second hard mask. Subsequently, using the patterned first hard mask as an etch mask, a second etch process is performed to transfer the first trench patterns and the second trench patterns into the substrate.

Method of manufacturing independent depth-controlled shallow trench isolation

A method for fabricating a trench isolation structure is described. A trench is formed in a substrate. A liner layer is formed at least in the trench. A precursor layer is formed at least on the sidewalls of the trench. The precursor layer is converted to an insulating layer that has a larger volume than the precursor layer and fills up the trench.

Method for fabricating trench isolation structure

A method of forming a ring-type capacitor is provided. The method includes providing a substrate; forming a patterned mask layer on the substrate, the patterned mask layer defining a ring pattern; removing the substrate by using the patterned mask layer as a mask to form a ring-type trench in the substrate; the ring-type trench including an inner wall and an outer wall; and forming a capacitor structure on the inner wall and the outer wall of the ring-type trench.

Method of forming a trench capacitor

A method for forming a ring pattern is disclosed. The ring pattern has a first wall and a second wall. The method includes the following steps: (a) providing a substrate; (b) forming a dielectric layer on the substrate; (c) forming a first patterned photoresist layer on the dielectric layer, the first patterned photoresist layer defining the first wall; (d) etching the dielectric layer to a predetermined depth by using the first patterned photoresist as a mask, and then removing the first patterned photoresist layer; (e) forming a second patterned photoresist layer on the dielectric layer, the second patterned photoresist layer defining the second wall; (f) etching the dielectric layer by using the second patterned photoresist layer as a mask so as to form the ring pattern having the first wall and the second wall.

Method for forming ring pattern

A method for forming a bit-line contact plug includes providing a substrate including a transistor which includes a gate structure and a source/drain at both sides of the gate structure; forming a conductive layer, a bit-line contact material layer and a hard mask layer; performing an etching process using the conductive layer as an etching stop layer to etch the bit-line contact material layer and the hard mask layer and forming the bit-line contact plug on the source/drain. A transistor structure includes a gate structure and a source/drain at both sides of the gate structure, a conductive layer covering part of the gate structure and connected to the source/drain, and a bit-line contact plug disposed on the conductive layer and directly connected to the conductive layer.

Method for forming bit-line contact plug and transistor structure

A method of fabricating an isolation shallow trench contains providing a substrate with at least a deep trench, forming a cap layer on the upper portion of the deep trench, forming a crust layer on a portion of the cap layer, defining a trench extending through the cap layer and the conductive layer, and forming an isolation layer in the shallow trench.

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Taoyuan County, Taiwan

Jen-Jui Huang