National Central University

Tekcore Co., Ltd.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Delta Electronics, Inc.

Epistar Corporation

Tsinghua University

National Applied Research Laboratories

National Taiwan University

Tekcove Co., Ltd

Jen-Inn Chyi

Chia-Ming Lee

Geng-Yen Lee

Hung-Cheng Lin

Hsueh-Hsing Liu

Szu-Hung Chen

Shih-Chang Lee

Ta-Cheng Hsu

Rong-Ren Lee

Yu-Lin Wang

Meng-Yang Chen

Shih-Pang Chang

Wen-Kuan Yeh

Yu-Chuan Liu

Guang-Li Luo

Hung-Chih Lu

I-Ling Chen

Clement Hsingjen Wann

Chih-Hsin Ko

Cheng-Hsien Wu

Chun-Chieh Yang

Indu Sarangadharan

Sheng-Yu Wang

Heng-Kuang Lin

Pei-Chin Chiu

Han-Chieh Ho

Guan-Ting Chen

Gwo-Bin Lee

Jin-Wei Shi

Ching-Chuan Shiue

Shih-Peng Chen

Jinn-Kong Sheu

Chun-Kai Wang

Chia-Cheng Liu

Juei-Nai Kwo

Yu-Jiun Shen

Ya-Yu Yang

Ming-Hwei Hong

Shang-Ju Tu

Tai-Kang Shing

Jui-Lin Chu

Tsung-Cheng Chang

Chia-Ho Chu

Mao-Jen Wu

Shu-Chu Shiesh

Chen-Pin Hsu

Tun-Wen Pi

Wei-Sheng Lin

Jung-Ying Fang

Bo-Shiang Wang

Hui-Ling Lin

Cheng-Han Tsou

Jiun-Ming Chen

Wei-Kai Shen

Lung-Chieh Cheng

Hsien Yu Lin

Peng-Ren Chen

Shu-Han Cheng

Abiral Regmi

Cheng-Hiong Chen

Wei-Sheng Liu

A method of making a semiconductor device includes: providing a substrate; forming an insulating layer on the substrate; forming a first trench in the insulating layer; forming a first semiconductor layer in the first trench; and removing a portion of the insulating layer to expose the first semiconductor layer.

Heterogeneously integrated semiconductor device and manufacturing method thereof

A high electron mobility transistor, includes a substrate; a channel layer formed on the substrate; a barrier layer formed on the channel layer; a source electrode and a drain electrode formed on the barrier layer; a depletion layer formed on the barrier layer and between the source electrode and the drain electrode, wherein a material of the depletion layer comprises boron nitride or zinc oxide; and a gate electrode formed on the depletion layer.

High electron mobility transistor and methods for manufacturing the same

Semiconductor contact structures, a semiconductor device including the semiconductor contact structures, and a method for forming the same are disclosed. In an embodiment, a semiconductor device includes a channel layer on a substrate; an interface layer on the channel layer, the interface layer including titanium (Ti), the interface layer contacting the channel layer; and a contact metal layer over the interface layer, the contact metal layer including aluminum silicon copper alloy (AlSiCu).

Ohmic contact structure, semiconductor device including an ohmic contact structure, and method for forming the same

A heterogeneously integrated semiconductor device includes a substrate comprising a first material; a recess formed within the substrate and having a bottom portion with a first width, a top portion with a second width and a middle portion with a third width larger than the first width and the second width; and a first semiconductor layer filled in the bottom portion and including a second material different from the first material.

A biosensor includes a transistor and a reactive electrode. The transistor has a source, a drain and a gate surface disposed therebetween. The reactive electrode is spaced apart from the gate surface of the transistor, has a receptor immobilized thereon for specific binding with an analyte in a liquid sample, and is configured to contact the liquid sample together with the gate surface of the transistor.

Biosensor and method for analyzing analyte concentration in a liquid sample

In one aspect of the present disclosure, a semiconductor device includes a channel layer, an AlInN layer on the channel layer with a thickness of t1, and a reverse polarization layer on the AlInN layer with a thickness of t2. The thickness is 0.5&#xd7;t1&#x2264;t2&#x2264;3&#xd7;t1. In another aspect of the present disclosure, a method of manufacturing a semiconductor device is provided. The method including: forming a channel layer on a substrate; forming an AlInN layer on the channel layer with a thickness of t1; and forming a reverse polarization layer on the AlInN layer with a thickness of t2. The thickness is 0.5&#xd7;t1&#x2264;t2&#x2264;3&#xd7;t1.

Semiconductor device and method of fabricating the same

A heterogeneously integrated semiconductor devices includes a base substrate; a Ge-containing film formed on the base substrate; a PMOSFET transistor having a first fin formed on the Ge-containing film; and a NMOSFET transistor having a second fin formed on the Ge-containing film; wherein the PMOSFET transistor and the NMOSFET transistor compose a CMOS transistor, and the first fin comprises Ge-containing material and the second fin comprises a Group III-V compound.

A method for analyzing concentration of a cardiovascular disease (CVD) biomarker in a liquid sample includes: applying the liquid sample to a biosensor, the biosensor including a transistor having a drain, a source, and a gate terminal disposed between the gate and the source, and a reactive electrode spaced apart from the gate terminal of the transistor and having a receptor immobilized thereon for specific binding with the CVD biomarker, the liquid sample being in contact with the gate terminal and the reactive electrode; applying a voltage pulse between the reactive electrode and the source, the voltage pulse having a pulse width; monitoring a response current in response to the voltage pulse; and analyzing the response current.

Method for detecting cardiovascular disease biomarker

A viscosity measurement system, which is for measuring the viscosity of a fluid, comprises a transistor-type viscosity sensor, an electrical measurement unit, and a processing unit. The transistor-type viscosity sensor includes a semiconductor structure, a source terminal, and a drain terminal. The semiconductor structure includes a GaN layer and an AlGaN layer disposed on the GaN layer. The portion of the semiconductor structure that is between the source terminal and the drain terminal has a gate region, which has an exposed surface for being in contact with the fluid. The electrical measurement unit is in electrical connection with the source terminal and the drain terminal and for measuring an electronic signal of the semiconductor structure. The processing unit is coupled to the electrical measurement unit and for determining the viscosity of the fluid according to the electronic signal measured.

Transistor-type viscosity sensor, and viscosity measurement system and viscosity measuring method using the same

A diode device including a III-N compound layer is provided. The III-N compound layer has a channel region therein. A cathode region is located on the III-N compound layer. A first anode region is located on the III-N compound layer and extends into the III-N compound layer. The bottom of the first anode region is under the channel region. A second anode region is located on the III-N compound layer between the cathode region and the first anode region, and extends into the III-N compound material layer. The second anode region includes a high-energy barrier region. The high-energy barrier region adjoins a sidewall of the first anode region. A method for manufacturing a diode device is also provided.

Diode device and method for manufacturing the same

Disclosed is a wafer comprising a first layer of GaSb grown on a GaSb substrate by molecular beam epitaxy (MBE), an oxide layer deposited on the surface of the first layer, and a cap layer deposited on the surface of the oxide layer. The wafer was capped with an arsenic (As) layer after the growth of the first layer. The As layer was removed from the wafer before the oxide layer was deposited on the surface of the first layer. Also disclosed is a method of forming a wafer. The method comprises growing a first layer of GaSb on a GaSb substrate by MBE, capping the wafer with an As layer after the growth of the first layer, removing the As layer from the wafer, depositing an oxide layer on the surface of the first layer, and depositing a cap layer on the surface of the oxide layer.

Using molecular beam epitaxy in a semiconductor structure with a high K/GaSb interface

A field effect transistor device is provided by the invention. The field effect transistor device includes: a substrate; a buffer layer, a channel layer, and a first barrier layer sequentially disposed on the substrate; a two-dimensional electron gas controlling layer disposed on the first barrier layer; a second barrier layer disposed on the two-dimensional electron gas controlling layer, wherein the second barrier layer has a recess passing through the second barrier layer; and a gate electrode filled into the recess and separated from the second barrier layer and the two-dimensional electron gas controlling layer by an insulating layer.

Field effect transistor device

A method for fabricating a mesa sidewall with a spin coated dielectric material and a semiconductor element fabricated by the same are provided in the present invention. The method includes the steps of: disposing an object on a semiconductor substrate; performing a spin coating process to coat with a liquid dielectric material; performing a drying process to dry the liquid dielectric material; performing a first etching process to remove an upper part of the dried dielectric material to expose a metal part (unaffected by ion bombardment) of the object; performing a deposition process to insulate the metal part (unaffected by ion bombardment) of the object; and performing a second etching process to form a semiconductor element with a mesa sidewall.

Method for fabricating mesa sidewall with spin coated dielectric material and semiconductor element thereof

A semiconductor device including a substrate, a heterojunction body, a passivation layer, a source contact, a drain contact, and a gate contact. The heterojunction body disposed on or above the substrate includes a first semiconductor layer, a mask layer, a regrowth layer, and a second semiconductor layer. The first semiconductor layer is disposed on or above the substrate. The mask layer is disposed on or above a portion of the first semiconductor layer. The regrowth layer disposed on the first semiconductor layer and adjacent to the mask layer includes a main portion and at least one inclined portion. The second semiconductor layer is disposed on the mask layer and the regrowth layer. The passivation layer is disposed on the second semiconductor layer. The gate contact is disposed on the passivation layer, between the source contact and the drain contact, and at least above the inclined portion of the regrowth layer.

Semiconductor device and manufacturing method thereof

A growth method for reducing defect density of GaN includes steps of: sequentially forming a buffer growth layer, a stress release layer and a first nanometer cover layer on a substrate, wherein the first nanometer cover layer has multiple openings interconnected with the stress release layer; growing a first island in each of the openings; growing a first buffer layer and a second nanometer cover layer on the first island; and growing a second island to form a dislocated island structure. Thus, through the first nanometer cover layer and the second nanometer cover layer, multiple dislocated island structures can be directly formed to reduce manufacturing complexity as well as increase yield rate by decreasing manufacturing environment variation. Further, the epitaxial lateral over growth (ELOG) approach also effectively enhances characteristics of GaN optoelectronic semiconductor elements.

Growth method for reducing defect density of gallium nitride

Growing community of inventors

Taoyuan, Taiwan

Jen-Inn Chyi