Mediatek Corporation

Realtek Semiconductor Inc.

Jen-Huan Tsai

Chih-Hong Lou

Po-Chiun Huang

Shawn Min

Shih-Hsiun Huang

The invention provides a system improving signal handling, e.g., transmission and/or processing. In an embodiment, the system may include a filter circuit, a magnitude bit truncation circuit and a utility circuit. The filter circuit may be coupled to a target signal which contains one or more desired signals at one or more interested bands, for attenuating each said interested band to form a filtered signal. The magnitude bit truncation circuit may be coupled to the filter circuit, for truncating one or more bits of each sample of the filtered signal to form a truncated signal. The utility circuit may be coupled to the magnitude bit truncation circuit, for handling the truncated signal to implement handling of the target signal, so as to reduce resource requirement and enhance error tolerance comparing with directly handling the target signal.

System improving signal handling

The invention provides a sigma-delta modulator (SDM) and associated system improving spectrum efficiency of wired interconnection. The SDM may comprise a main circuit for transferring an aggregated signal by a signal transfer function, and a noise shaping circuit for shaping noise away from a low-pass band by a modified noise transfer function. A frequency response of the modified noise transfer function may have a notch at a passband, and the passband may not overlap with the low-pass band.

Sigma-delta modulator and associated system improving spectrum efficiency of wired interconnection

The invention provides an analog-to-digital converter (ADC) converting an input signal to an output signal. The ADC may comprise a main circuit and a comparator coupled to the main circuit. The main circuit may: transfer the input signal by an input transfer block, filter an error signal by a loop filter, and combine the transferred input signal and the filtered error signal to form a combined signal. The comparator may quantize the combined signal to provide the output signal, wherein the error signal may reflect a difference between the combined signal and the output signal.

Analog-to-digital converter

Circuits and methods for current recycling in signal buffers for switched capacitor circuits are described. A signal buffer may be coupled to an impedance element, such as a resistor, configured to provide a desired reference voltage to the switched capacitor circuit. In some embodiments, a portion of the power absorbed by the impedance element may be recycled to power one or more additional circuit. Such additional circuit(s) may include active elements. In some embodiments, the switched capacitor circuit is part of an analog-to-digital converter. In some embodiments, the additional circuit(s) are also part of the analog-to-digital converter.

Circuits for current recycling and related methods

An exemplary quantizer includes a multi-bit analog-to-digital converter (ADC) and a first digital-to-analog converter (DAC) feedback circuit. The multi-bit ADC has an internal DAC associated with comparison of each sampled analog input of the multi-bit ADC. The multi-bit ADC converts a currently-sampled analog input into a first digital output. A first noise-shaped truncation output is derived from the first digital output. The first DAC feedback circuit transfers a first truncation residue associated with the first noise-shaped truncation output to the internal DAC. The transferred first truncation residue is reflected in comparison of a later-sampled analog input of the multi-bit ADC via the internal DAC.

Analog-to-digital converter with embedded noise-shaped truncation, embedded noise-shaped segmentation and/or embedded excess loop delay compensation

A preamplifier circuit comprising six transistors is provided. The first transistor is coupled to a power supply line and the second transistor is coupled to a ground line. The first and second transistors are controlled by an enable signal. The third and fourth transistors are connected between the first and second transistors, for generating a first amplifier output signal in response to a first input signal. The fifth and sixth transistors are connected between the first and second transistors, for generating a second amplifier output signal in response to a second input signal. The first, third, and fifth transistors are of a first conductivity type, and the second, fourth, and sixth transistors are of a second conductivity type. The preamplifier circuit can be applied to any type of ADC that utilizes a comparator.

Preamplifier circuit and SAR ADC using the same

A predictive successive approximation register analog-to-digital conversion device and method are provided. A difference between two input signals of a comparator is detected according to a threshold less than or equal to &#xbd; of a voltage increment represented by one least significant bit (LSB). When a difference between a first analog signal and a second analog signal is less than a threshold, a detection circuit enables a bit in a digital signal corresponding to a comparison cycle to which the difference belongs to be forcedly decided to be a first value and predicts values of the remaining bits.

Predictive successive approximation register analog-to-digital conversion device and method

A successive approximation analog-to-digital converter (SAR ADC) includes a capacitor array and a comparator. The capacitor array has M capacitors which are arranged to perform capacitor switching operations sequentially, wherein a sum of capacitance values of the M capacitors is equal to (2&#x2212;1) unit capacitors, M&#x3e;N, and M and N are both positive integers. The comparator is arranged for comparing an output of the capacitor array and an analog input sequentially.

Successive approximation analog-to-digital converter using capacitor array with sub-capacitors configured by capacitor disassembling and related method thereof

A successive approximation (SAR) analog-to-digital converter for generating a digital signal of N bits is provided. The converter includes a capacitive digital-to-analog conversion circuit including an (N&#x2212;1)-th conversion unit to a first conversion unit. Each of the first conversion unit to the (N&#x2212;2)-th conversion unit includes a capacitor. The (N&#x2212;1)-th conversion unit comprises a number of sub-capacitors. Each of the sub-capacitors of the (N&#x2212;1)-th conversion unit has substantially the same capacitance with corresponding capacitor of the first conversion unit to the (N&#x2212;2)-th conversion unit. During the conversion process, the SAR control circuit, after generating the value of the most significant bit (MSB) of the digital signal, generates the value of the next bit by controlling the (N&#x2212;1)-th conversion unit. Then, the SAR control circuit repeatedly uses at least one of the sub-capacitors of the (N&#x2212;1)-th conversion unit to generate the value of other bits to perform self linear compensation.

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Hsinchu, Taiwan

Jen-Huan Tsai