Taiwan Semiconductor Manufacturing Comp. Ltd.

Jen-Hang Yang

Hui-Zhong Zhuang

Chun-Fu Chen

Pin-Dai Sue

Li-Chun Tien

Chih-Chiang Chang

Ta-Pen Guo

Shang-Chih Hsieh

Osamu Takahashi

Ming-Zhang Kuo

Chun-Hui Tai

Mi-Chang Chang

Hsien-Te Chen

Sang Hoo Dong

Su-Ya Lin

An antenna cell for preventing plasma enhanced gate dielectric failures, is provided. The antenna cell design utilizes a polysilicon lead as a gate for a dummy transistor. The polysilicon lead may be one of a group of parallel, nested polysilicon lead. The dummy transistor includes the gate coupled to a substrate maintained at V, either directly through a metal lead or indirectly through a tie-low cell. The gate is disposed over a dielectric disposed over a continuous source/drain region in which the source and drain are tied together. A diode is formed with the semiconductor substrate within which it is formed. The source/drain region is coupled to another metal lead which may be an input pin and is coupled to active transistor gates, preventing plasma enhanced gate dielectric damage to the active transistors.

Method for designing antenna cell that prevents plasma induced gate dielectric damage in semiconductor integrated circuits

Antenna cell design to prevent plasma induced gate dielectric damage in semiconductor integrated circuits

A circuit includes a logic gate and a latch. The logic gate is configured to receive a clock signal at a first input. The latch is disposed in a feedback loop of the logic gate and is configured to output a feedback signal to a second input of the logic gate in response to a signal output by the logic gate and the clock signal. The circuit is configured to output a pulsed signal based on one of a rising edge or a falling edge of the clock signal.

Pulse generator

A multiplexing circuit includes first and second tri-state inverters coupled to first and second data input nodes, respectively. The first and second tri-state inverters include first and second stacks of transistors, respectively, coupled between power supply and ground nodes. Each stack includes first and second PMOS transistors and first and second NMOS transistors. The first and second stacks include first and second dummy transistors, respectively.

Method and apparatus for improved multiplexing using tri-state inverter

This invention discloses a decoupling capacitor in an integrated circuit, comprising a plurality of dedicated PN diodes with a total junction area greater than one tenth of a total active area of functional devices for which the dedicated PN diodes are intended to protect, a N-type region of the dedicated PN diodes coupling to a positive supply voltage (Vdd), and a P-type region of the dedicated PN diodes coupling to a complimentary lower supply voltage (Vss), wherein the dedicated PN diodes are reversely biased.

Reverse-biased PN diode decoupling capacitor

This invention discloses a method for automatically adjusting cell layout height and transistor width of one type of MOS IC cells, the method comprising following steps of Boolean logic operations on at least one such cell: identifying one or more MOS transistor active areas (ODs) and one or more power ODs in an OD layer, expanding the MOS transistor ODs in a predetermined direction by a first predetermined amount, shifting the power ODs in the predetermined direction by a second predetermined amount, expanding one or more MOS transistor gate areas in the predetermined direction by a third predetermined amount, shifting one or more power OD contacts in the predetermined direction by approximately the second predetermined amount, and stretching one or more metal areas (Ms) in a metal layer that is directly coupled to the OD layer through contacts electronically, in the predetermined direction by a predetermined way.

Method for automatically modifying integrated circuit layout

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Yonghe, Taiwan

Jen-Hang Yang