Taiwan Semiconductor Manufacturing Comp. Ltd.

Jen-Chih Hsueh

Yi-Wei Chiu

Chih-Chang Hung

Tsung Fan Yin

Chih-Teng Liao

Chen-Wei Pan

Li-Te Hsu

Yu-Li Lin

Ying-Ting Hsia

Tsung-Fan Yin

Hsiu-Ling Chen

Rong-Yu Wu

Li-Feng Chu

Embodiments include methods and devices which utilize dummy gate profiling to provide a profile of a dummy gate which has narrowing in the dummy gate. The narrowing causes a neck in the dummy gate. When the dummy gate is replaced in a gate replacement process, the necking provides control of an etch-back process. Space is provided between the replacement gate and a subsequently formed self-aligned contact.

Transistor gate structure and process

A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

Semiconductor device and method

In a method of manufacturing a semiconductor device, a fin structure protruding from an isolation insulating layer disposed over a substrate is formed, a sacrificial gate dielectric layer is formed over the fin structure, a polysilicon layer is formed over the sacrificial gate dielectric layer, a mask pattern is formed over the polysilicon layer, and the polysilicon layer is patterned into a sacrificial gate electrode using the mask pattern as an etching mask. The sacrificial gate electrode has a narrow portion above a level of a top of the fin structure such that a width of the sacrificial gate electrode decreases, takes a local minimum, and then increases from the top of the fin structure.

Method of manufacturing a semiconductor device and a semiconductor device

A method for forming a semiconductor device structure is provided. The method includes forming a spacer layer and a dielectric layer over a substrate. The spacer layer has an opening exposing the substrate, and the dielectric layer surrounds the spacer layer. The method includes forming a metal silicon nitride layer over a sidewall and a bottom surface of the opening. The method includes forming a first work function metal layer over the metal silicon nitride layer. The method includes removing a first top portion of the first work function metal layer. The method includes, after the removal of the first top portion, removing a second top portion of the metal silicon nitride layer. The method includes forming a conductive layer in the opening. The method includes removing a third top portion of the conductive layer and a fourth top portion of the metal silicon nitride layer.

Semiconductor device structure and method for forming the same

Growing community of inventors

Kaohsiung, Taiwan

Jen-Chih Hsueh