Taiwan Semiconductor Manufacturing Comp. Ltd.

Jen-Chieh Liu

Meng-Fan Chang

Win-San Khwa

Jui-Jen Wu

Yi-Lun Lu

Tung-Ying Lee

Xinyu Bao

Jin Cai

Elia Ambrosi

Jui Jen Wu

A control circuit, a memory system and a control method are provided. The control circuit is configured to control a plurality of memory cells of a memory array. The control circuit comprises a program controller. The program is configured to program a first electrical characteristic distribution and a second electrical characteristic distribution of the memory cells according to error tolerance of a first bit of a data type. A first overlapping area between the first electrical characteristic distribution and the second electrical characteristic distribution is smaller than a first predetermined value.

Control circuit, memory system and control method

A memory test circuit is provided. The memory test circuit is disposed in a memory chip and electrically coupled to a memory macro of the memory chip. A high speed clock receives an input signal and an external clock signal. The input signal includes a plurality of test bits. A finite state machine controller provides a pattern type. A pattern generator generates and provides a test signal to at least one memory cell of the memory chip to write the test signal to the at least one memory cell based on the pattern type and the external clock signal. A test frequency of the test signal is determined based on the high speed clock. An output comparator outputs a comparison signal based on a difference between the test signal and a readout signal corresponding to the test signal read from the at least one memory cell.

Memory test circuit, memory chip, and testing method of memory chip

A circuit includes first and second data lines, a sense amplifier including first and second input terminals, a first p-type metal-oxide-semiconductor (PMOS) transistor coupled in series with a first capacitive device between the first data line and the second input terminal, a second PMOS transistor coupled in series with a second capacitive device between the second data line and the first input terminal, a third PMOS transistor coupled between the first data line and the first input terminal, a fourth PMOS transistor coupled between the second data line and the second input terminal, a first n-type metal-oxide-semiconductor (NMOS) transistor configured to selectively couple each of the first PMOS transistor and the first capacitive device to a ground node, and a second NMOS transistor configured to selectively couple each of the second PMOS transistor and the second capacitive device to the ground node.

Sense amplifier circuit and method

A circuit includes a sense amplifier, a first clamping circuit, a second clamping circuit, and a feedback circuit. The first clamping circuit includes first clamping branches coupled in parallel between the sense amplifier and a memory array. The second clamping circuit includes second clamping branches coupled in parallel between the sense amplifier and a reference array. The feedback circuit is configured to selectively enable or disable one or more of the first clamping branches or one or more of the second clamping branches in response to an output data outputted by the sense amplifier.

Memory devices, circuits and methods of adjusting a sensing current for the memory device

An integrated circuit includes a memory storage having bit cells, a write path switch configured to have a connection state determined by a reliability indicator, and a write driver having an input configured to receive an input data from a write terminal through either a first write path or a second write path. The input data received through the first write path is configured to be equal to the data at the write terminal, and the input data received through the second write path is configured to be a bitwise complement of the data at the write terminal. The reliability indicator is configured to be set based on a majority bit value in the data or based on a minority bit value in the data.

Non-volatile memory stored with encoded data

The disclosure provides a method for controlling a sense amplifier. The control device includes a latch circuit and a control circuit. The latch circuit receives a plurality of memory data signals from the sense amplifier, wherein the latch circuit respectively generates a plurality of reference data signals based on the plurality of memory data signals. The control circuit is coupled to the latch circuit, provides an enable signal to the sense amplifier in response to a pass gate signal of the sense amplifier, and stops providing the enable signal in response to at least one of the plurality of reference data signals, wherein the enable signal controls a sensing period of the sense amplifier.

Method for controlling sense amplifier and control device using the same

The sense amplifier circuit includes a differential amplifier, a first switch, and a second switch. The differential amplifier includes a first input node, a second input node, a first output node, and a second output node. The differential amplifier amplifies a voltage difference of the first output node and the second output node according to a first input voltage of the first input node and a second input voltage of the second input node. A control node of the first (second) switch is coupled to a control line, the first (second) switch is coupled to the first (second) input node, and the first (second) switch is coupled to the first (second) output node. The first (second) switch pre-charges the first (second) input node by a first (second) output voltage of the first (second) output node while the control line is received a select signal.

Sense amplifier circuit, memory circuit, and sensing method thereof

A memory test circuit is provided. The memory test circuit is disposed in a memory array and including: a test array, including test cells out of memory cells of the memory array; a write multiplexer, configured to selectively output one of a test signal and a reference voltage based on a write measurement signal, wherein the test signal is output to write into at least one test cell and the reference voltage is output to a sense amplifier; and a read multiplexer, configured to selectively receive and output one of a readout signal corresponding to the test signal and an amplified signal based on a read measurement signal, wherein the readout signal is read from the at least one test cell and the amplified signal is obtained for a read margin evaluation from the sense amplifier by amplifying a voltage difference between the readout signal and the reference voltage.

Memory test circuit, memory array, and testing method of memory array

A memory device includes a set of word lines, a set of bit lines, a source line having first and second source line contacts, a set of transistors serially coupled between the first and second source line contacts of the source line, and a set of data storage elements. The set of transistors has gates coupled to corresponding word lines in the set of word lines. Each data storage element in the set of data storage elements is coupled between a common terminal of a corresponding pair of adjacent transistors in the set of transistors, and a corresponding bit line in the set of bit lines.

Memory device, integrated circuit device and method

A method of storing a data into a memory storage having bit cells. The method includes identifying each of the binary one and the binary zero in the data as either a majority bit value or a minority bit value based on the probability of finding the binary one in the data or based on the probability of finding the binary zero in the data. In the method, a bit of the data is stored into the bit cell as the more preferred state if the bit of the data has the majority bit value, and a bit of the data is stored into the bit cell as the less preferred state if the bit of the data has the minority bit value.

Method of data encoding in non-volatile memories

A system includes a memory cell array including multi-level cells, an input data scramble circuit configured to receive input data and match lower error tolerant bits with higher error tolerant bits to provide matched bit sets, wherein each of the matched bit sets includes at least one lower error tolerant bit and at least one higher error tolerant bit, and a write driver configured to receive the matched bit sets and store each of the matched bit sets into one memory cell of the multi-level cells.

Multi-level cell data encoding

A device includes a write bit line and a read bit line extending in a first direction, and a write word line and a read word line extending in a second direction perpendicular to the first direction. The device further includes a memory cell including a write transistor and a read transistor. The write transistor includes a first gate connected to the write word line, a first source/drain connected to the write bit line, and a second source/drain connected to a data storage node. The read transistor includes a second gate connected to the data storage node, a third source/drain connected to the read bit line, and a fourth source/drain connected to the read word line.

High-density memory cells and layouts thereof

A method of storing an input data of a data set into a memory storage having bit cells. The method includes determining a bit value of a characterization bit in the input data. The method also includes writing each of remaining bits in the input data into one of the bit cells as a first state if the characterization bit has a first value, and writing each of remaining bits in the input data into the bit cells as a second state if the characterization bit has a second value that is complement to the first value. In the method, either reading the bit cell with the first state consumes less energy than reading the bit cell with the second state or the bit cell with the first state has less retention errors than the bit cell with the second state.

Method of storing data in memories

A circuit includes a reference voltage node, first and second data lines, a sense amplifier, first and second switching devices coupled between the first and second data lines and first and second input terminals of the sense amplifier, third and fourth switching devices coupled between the first and second data lined and first and second nodes, fifth and sixth switching devices coupled between the first and second nodes and the reference voltage node, and first and second capacitive devices coupled between the first and second nodes and second and first input terminals. Each of the first through fourth switching devices is switched on and each of the fifth and sixth switching devices is switched off in a first operational mode, and each of the first through fourth switching devices is switched off and each of the fifth and sixth switching devices is switched on in a second operational mode.

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Hsinchu, Taiwan

Jen-Chieh Liu