Taiwan Semiconductor Manufacturing Comp. Ltd.

Jen-Chi Chang

Ding-I Liu

Po-Hsiung Leu

Wen-Long Lee

Kai-Shiung Hsu

Chun-Li Lin

Ming-Shiou Kuo

Chi-Ching Lo

Tzu-Chun Lin

Ho-Ta Chuang

The present disclosure provides a method of making an integrated circuit. The method includes forming a gate stack on a semiconductor substrate; forming a stressed contact etch stop layer (CESL) on the gate stack and on the semiconductor substrate; forming a first dielectric material layer on the stressed CESL using a high aspect ratio process (HARP) at a deposition temperature greater than about 440 C to drive out hydroxide (OH) group; forming a second dielectric material layer on the first dielectric material layer; etching to form contact holes in the first and second dielectric material layers; filling the contact holes with a conductive material; and performing a chemical mechanical polishing (CMP) process.

Interlayer dielectric structure with high aspect ratio process (HARP)

A plasma reactor includes an enclosure having a top and a bottom and defining a processing chamber. Inlets are formed in the enclosure for injecting process gas into the chamber. An outlet is formed in the enclosure for withdrawing gas from the chamber. A platform is positioned to support a wafer in the chamber above the bottom. A plurality of coils is positioned above the top of the chamber. Each coil is coupled to a radio frequency generator.

High density plasma reactor with multiple top coils

A semiconductor structure and a method for forming the same are provided. The semiconductor structure includes a first gate structure formed over a substrate. The semiconductor structure includes a first spacer formed on a sidewall of the first gate structure. In addition, a top surface of the first spacer is parallel to a top surface of the substrate.

Gate structure having spacer with flat top surface and method for forming the same

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Hsinchu, Taiwan

Jen-Chi Chang