Samsung Electronics Co., Ltd.

Jei-Hwan You

Sei-seung Yoon

Myong-Jae Kim

Dong-soo Jun

A self-refresh method and refresh control circuit of a semiconductor memory device, wherein after the self-refresh mode starts, the burst refresh mode is performed prior to the self-refresh mode; or the self-refresh mode is performed immediately after going into the self-refresh mode, and the burst refresh mode is performed at the completion of the self-refresh mode, and then the burst refresh mode is converted to the normal access mode; or the burst refresh mode is performed before and after the self-refresh mode, thereby shortening a refresh regulation time and securing a stable refresh of the memory cells.

Self-refresh method and refresh control circuit of a semiconductor

The present invention relates to a semiconductor memory device and more particularly to a power supply voltage detecting circuit of a semiconductor memory device which senses a voltage level of the power supply voltage. A power supply voltage detecting circuit of the present invention includes a circuit for generating a power supply voltage detecting signal by receiving a power supply voltage and a control circuit for generating a control signal in order to operate the circuit for generating the power supply voltage detecting signal when being in a specific mode state. The power supply voltage detecting circuit according to the present invention can reduce power consumption by cutting off a standby-current, since the power supply voltage detecting circuit is enabled during an activation of a chip. This allows the output signal of the power supply voltage detecting circuit to have an accurate voltage level of a power supply voltage or a ground voltage, so that chip operation speed can be improved and the effectiveness of the chip can be improved by removing noises.

Supply voltage detecting circuit of a semiconductor memory device

A parallel test circuit is provided in a semiconductor memory chip for use during both a wafer test and a package test. The parallel test circuit operates to automatically reduce the number of test output pins associated with a single package test to thereby increase the number of packages that can be tested simultaneously. The parallel test circuit includes a selector for limiting the number of output pads which may be activated during a package test run. The selector is responsive to a wafer test enable signal, from a selection control circuit, to control output pad selection.

Parallel test circuit for use in a semiconductor memory device

A semiconductor memory device with data retention function to retain data is provided with a sense amplifier control signal generating circuit comprising a switching circuit controlled by a data retention mode detection signal so as to make the time interval between enabling of a word line and starting of an N- or P-type sense amplifier longer in data retention mode than in normal mode. Thus the inventive circuit generates a sense amplifier control signal whose delay time differs in the normal and data retention modes, so that the data retention mode is performed without influencing the operational speed, the charge sharing is sufficiently achieved in the data retention mode, and the direct current flowing is prevented.

Data retention mode control circuit

A refresh timer suitable for use in a semiconductor memory device which has a refresh mode of operation which is enabled by a refresh enable clock signal, and which utilizes an operating voltage having a plurality of different operating levels, Vi, where i=1-n, and n is an integer equal to or greater than two. The refresh timer includes a first circuit responsive to the operating voltage for generating a plurality of output voltage signals corresponding to the plurality of different operating voltage levels, respectively. The first circuit includes a plurality of individual voltage detection circuits corresponding to the plurality of different operating voltage levels, respectively, with each ith one of the voltage detection circuits being adapted to detect whether the operating voltage is at the corresponding ith level, and to drive the corresponding ith one of the output voltage signals high when it is detected that the operating voltage is at the corresponding ith level. The refresh timer also includes additional circuitry responsive to the refresh enable clock signal and the ith one of the output voltage signals which was last driven high by the first circuit, for generating a refresh cycle time control signal having a constant period, regardless of the level of the operating voltage.

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Suwon, South Korea

Jei-Hwan You