Samsung Electronics Co., Ltd.

Jei-hwan Yoo

Moon-hae Son

Byung-chul Kim

Ho-Sung Song

Jae-Woong Lee

A semiconductor memory device including a redundancy circuit having latch cells is provided. In the semiconductor memory device, memory cells are selected in memory cell blocks each having a plurality of memory cells arrayed in columns and rows. Data of the selected memory cells is input to or output from the memory cell blocks via data lines. The semiconductor memory device includes a row decoder, a sub word line driver, latch cells, fuse boxes, a latch cell control unit, and a switch unit. The row decoder decodes a row address and generates a word line enable signal for selecting the word lines of a group of memory cells among memory cells. The sub word line driver is connected to the word line enable signal, and drives the selected memory cells. The latch cells are arranged along the data lines. Each of the fuse boxes has a plurality of fuses which are programmed in accordance with a defective cell address in the memory cell block. The latch cell control unit generates a latch cell selection signal in response to the output signal of each of the fuse boxes, and selects latch cells. The switch units connect the selected latch cells to the data lines in response to the latch cell selection signal.

Semiconductor memory device including redundancy circuit adopting latch cell

A semiconductor memory device having a row redundancy scheme in which the time to enable a word line during a normal path is less than that of a conventional device, to enhance the operation speed of a memory chip, and the number of common redundancies are maximized to enhance the redundancy capability, and a method for curing a defective cell. The semiconductor memory device has a plurality of global blocks, each of which includes a plurality of unit matrixes having a normal block and a redundancy block, a normal division word line driver, a redundancy division word line driver, a main decoder and an auxiliary decoder. In the main decoder, an output signal is selectively activated according to a row address signal regardless of using the redundancy cell. Also, in the auxiliary decoder, when a corresponding global block is selected according to the row address signal for selecting a global block in a normal operation mode or a redundancy scheme of the corresponding block is used in the redundancy operation mode, an output signal is selectively activated according to the row address signal.

Semiconductor memory device having improved row redundancy scheme and method for curing defective cell

Integrated circuit memory devices include one or more input receivers that have a reference voltage input terminal. A conductor electrically couples the reference voltage input terminals to a reference voltage, and a capacitor is connected between the conductor and a first ground voltage. Preferably, the location of the connection between the capacitor and the conductor is selected in accordance with the electrical characteristics of the input receivers. Accordingly, the capacitor may reduce fluctuations or noise in the reference voltage applied to the reference voltage input terminals of the input receivers. The fluctuations or noise in the reference voltage may cause the input characteristics and/or the set-up and hold times of the input receivers to vary with respect to one another. A reduction in fluctuations or noise in the reference voltage may result in more consistent input characteristics among the input receivers and more consistency in the set-up and hold times.

Integrated circuit memory devices having reduced susceptibility to reference voltage signal noise

Integrated circuit memory devices include first and second spaced-apart memory banks in an integrated circuit substrate. A pad block in the integrated circuit substrate is located between the first and second spaced-apart memory banks. An input/output block in the integrated circuit substrate is connected to the pad block to receive input data from external of the integrated circuit memory device via the pad block and to transmit output data to external of the integrated circuit memory device via the pad block. A delay locked loop in the integrated circuit substrate is responsive to an external clock signal to generate an internal clock signal. An interface logic block in the integrated circuit substrate is responsive to the internal clock signal to control the first and second memory banks and the input/output block in response to the internal clock signal. A single data shift block in the integrated circuit substrate is located between the pad block and one of the first and second spaced-apart memory banks. The single data shift block is connected to the input/output block by a first plurality of lines and to both of the first and second memory banks by a second plurality of lines that is an integer multiple of the first plurality. The single data shift block converts serial data on the first plurality of lines to parallel data on the second plurality of lines and converts parallel data on the second plurality of lines to serial data on the first plurality of lines. The invention may be used in any integrated circuit memory device. However, the invention is preferably used in a packet type integrated circuit memory device that operates on packets of data address and control signals, such as a Rambus integrated circuit memory device.

Integrated circuit memory devices including a single data shift block

Integrated circuit memory devices can reduce write time during a write cycle of a parallel bit test mode. The memory devices include a simultaneous column select line activation circuit that simultaneously activates at least two of the plurality of column select lines during a write cycle of a parallel bit test mode. Therefore, during the write cycle, at least two bit lines are simultaneously connected to one input and output line since at least two column select lines are simultaneously activated by the simultaneous column select line activation circuit. Accordingly, data is simultaneously written to the memory cells connected to at least two bit lines through the input and output line.

Integrated circuit memory devices and controlling methods that

A semiconductor memory device is tested by sequentially coupling a plurality of global input/output lines to a comparator which compares data bits from the global input/output lines sequentially rather than in parallel so as to reduce the number of output sense amplifiers. This reduces both the chip area, and the excessive current consumption caused by large numbers of sense amplifiers operating in parallel. The memory device includes a plurality of global input/output lines coupled to a memory cell array to receive data from the memory cell array. A global line select circuit generates sequential global line select signals during a test operation. A plurality of switch circuits selectively couples data from the global input/output lines to a sense amplifier responsive to the global line select signals. A comparator coupled to the output port of the sense amplifier sequentially compares a sequence of test data output from the sense amplifier and generates a result signal during the test operation.

High speed test circuit for a semiconductor memory device

A circuit and method are shown for controlling a redundant memory cell of an integrated memory circuit. The circuit includes a decoder, a precharge enable unit, a redundant controller, a redundant enable signal generator, and a redundant memory cell array. The precharge enable unit is connected to the decoder, and responds to a precharge enable signal by precharging the output terminal of decoder. The decoder responds to a first row address signal by discharging the output terminal of the decoder unless the value of the row address signal corresponds to a programmed address of the decoder. The redundant enable signal generator samples the voltage level of the output terminal of the decoder under control of a redundant control signal of the redundant controller in order to generate a redundant cell enable signal. The redundant controller generates the redundant control signal in response to a second row address signal, where the redundant controller delays the redundant control signal by a predetermined time interval in response to a stress test signal which is active during a stress test in order to allow the decoder sufficient time to discharge the output terminal during the stress test. The redundant memory cell array is connected to the redundant enable signal generator and responds to the redundant enable signal.

Circuit and method for controlling a redundant memory cell in an

There is disclosed a semiconductor memory device that has a memory-cell array with memory cells arranged in a matrix, bit-line sense amplifiers connected to bit lines of the memory-cell array, a row address predecoder performing decoding of some of row address signals in response to a system clock, and a plurality of banks having an output line of the row address predecoder in common, includes: a row strobe buffer connected to an external system and producing a first control signal for selecting corresponding banks in response to the system clock, a row address strobe signal, and a bank selection address signal and for controlling generation of a row address sampling control signal; a row address sampling control signal generating circuit producing the row address sampling control signal in a predetermined period of time in response to generation of the first control signal produced by the row strobe buffer in order to control word-line activating and precharging operations; and a row decoder latching an output signal obtained by predecoding a row address with the output signal of the row address sampling control signal generating circuit.

Integrated circuit memory devices including a plurality of row latch

Semiconductor memory device with multibank structure

A test control circuit and method for performing a standardized test in a semiconductor memory device which has a structure such that it is difficult to perform a test operation using a standardized test mode. The test control method of a semiconductor memory device includes the steps of: arranging in the memory device a fuse capable of being electrically blown; receiving a plurality of external input signals applied to the memory device; generating a blocking signal based on the plurality of external input signals and the status of the electrical fuse; generating a parallel test enable signal based on the blocking signal and the plurality of external input signals, wherein, when the blocking signal is of a first logic level, the parallel test enable signal will indicate performance under either a parallel test mode or a normal operation mode based on the plurality of external input signals, and when the blocking signal is of a second logic level, the fuse is blown and the parallel test enable signal permanently indicates operation in a normal opreration mode.

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Kyungki-do, South Korea

Jei-hwan Yoo