Shenzhen China Star Optoelectronics Technology Co., Ltd.

Jehao Hsu

Xiaohui Yao

Jingfeng Xue

Caiqin Chen

Chengcai Dong

Minghung Shih

Jing-feng Xue

Cheng-hung Chen

Zui Wang

Chenghung Chen

Qibiao Lv

Chihhsien Li

A thin-film transistor (TFT) array substrate is provided. The TFT array substrate is structured to change the way that sub-pixels are arranged so that during a displaying period of a frame of image, the sub-pixels that have inconsistent brightness/darkness become alternate with each other spatially so that a displaying defect of vertical bright/dark lines can be improved and the overall resistance of the data line can be reduced to thereby reduce resistance-capacitance delay and prevent incorrect charging at a tail end of a scan line or a data line.

TFT array substrate

A panel inspection apparatus and a display panel are provided in the present invention. The panel inspection apparatus includes a data line detecting circuit and a scan line detecting circuit. The data line detecting circuit includes a data line detection switch, a control line of the data line detection switch, and a data line of the data line detection switch. The scan line detecting circuit includes a scan line detection switch, a control line of the scan line detection switch, and a data line of the scan line detection switch. The present invention further provides a display panel. The panel inspection apparatus does not need to be removed after detection of the panel in accordance with the panel inspection apparatus and the display panel of the present invention. Therefore, production costs of the display panel are reduced, and productivity of the display panel is improved.

Panel inspection apparatus and display panel

The present invention provides a thin-film transistor (TFT) array substrate. The TFT array substrate is structured to change the way that sub-pixels are arranged so that during a displaying period of a frame of image, the sub-pixels that have inconsistent brightness/darkness become alternate with each other spatially so that a displaying defect of vertical bright/dark lines can be improved and the overall resistance of the data line can be reduced to thereby reduce resistance-capacitance delay and prevent incorrect charging at a tail end of a scan line or a data line.

The present invention provides a TFT array substrate structure, which includes first and second gates (), a semiconductor layer (), first and second sources (), and first and second drains (). The first gate () and the first drain () are arranged to overlap in space so as to form a first overlapping zone (D). The second gate () and the second drain () are arranged to overlap in space so as to form a second overlapping zone (E). The first gate () has a first edge () corresponding to the first overlapping zone (D). The second gate () has a second edge () corresponding to the second overlapping zone (E). The first edge () and the first drain () intersect in space in an inclined manner. The second edge () and the second drain () intersect in space in an inclined manner. When the first and second drains () are moved relative to the first and second gates (), areas of the first overlapping zone (D) and the second overlapping zone (E) undergo identical change.

TFT array substrate structure

The present invention provides an exposure apparatus and an exposure method. The method comprises: utilizing an exposure light source to provide light rays to the photo-resist layer; and utilizing a reflective plate to reflect the light rays passing through the photo-resist layer and the transparent substrate back to the photo-resist layer. The present invention can reduce a line space of a pattern of the photo-resist layer.

Exposure apparatus and exposure method

The present invention provides a patterned vertical alignment (PVA) pixel electrode comprising: a first electrode in the form of a '' or '' shape disposed on a TFT array substrate; and a second electrode in the form of a &#x201c;&#x201d; or &#x201c;&#x201d; shape corresponding to the first electrode and disposed on a CF substrate, wherein the first electrode and/or the second electrode includes ITO slits with unequal length which are disposed between the fringes of the first electrode and the second electrode for improving a display quality of the pixel. The present invention further provides a liquid crystal display (LCD) apparatus. The PVA pixel electrode and the LCD apparatus using the same can raise a transmittance and a display quality of the pixel.

PVA pixel electrode and liquid crystal display apparatus using the same

A pixel driving method of a liquid crystal display (LCD) device, the LCD device comprising a first stage pixel, a second stage pixel, a first transistor, a second transistor, a third transistor, a first scan line, a second scan line, a plurality of data lines, a main pixel electrode, a sub pixel electrode, and a share capacitance, and the pixel driving method comprising the following steps: A step of driving the first scan line during the first driving period to charge the main pixel electrode and the sub pixel electrode of the first stage pixel, a step of ceasing to drive the first scan line during the second driving period to reduce voltages of the main pixel electrode and the sub pixel electrode of the first stage pixel, a step of driving the second scan line during the third driving period to turn on the third transistor of the first stage pixel, and a step of ceasing to drive the second scan line during the fourth driving period and pulling down the voltages of the main pixel electrode and the sub pixel electrode of the first stage pixel by implementing the share capacitance, which is connected with the third transistor during the third and the fourth driving period.

Liquid crystal display device and a pixel driving method thereof

A patterned vertical alignment (PVA) pixel electrode is disclosed. The PVA pixel electrode includes a first electrode and a second electrode. The first and second electrodes form a pre-tilt angle with respect to a periphery of the pixel. By disposing unequal lengths of indium-tin oxide (ITO) gaps at a periphery of the first and second electrodes, a distance between the first and second electrodes gradually becomes shortened from the center of the pixel outwards. The ITO gaps which are disposed at the periphery of a thin film transistor (TFT)-array substrate and/or a color filter (CF) are adjusted for eliminating a fringe field effect in the present invention, which a transmittance on the pixel regions is improved and an effect of image display quality is enhanced.

Patterned vertical alignment pixel electrode

A liquid crystal display apparatus includes scan lines, data lines perpendicular to the scan lines, a first pixel, a second pixel adjacent to the first pixel, and a black matrix layer. The first pixel includes a first main pixel and a first sub pixel. The first main pixel and the first sub pixel are arranged along a direction of the scan line. The second pixel includes a second main pixel and a second sub pixel. The second main pixel and the second sub pixel are arranged along the direction of the scan line. The black matrix layer covers the first pixel and the second pixel. The black matrix layer covers portions of the first main pixel, the first sub pixel, the second main pixel, and the second sub pixel. The first pixel and the second pixel are arranged along a direction of the data line.

Liquid crystal display apparatus and three-dimensional display apparatus

The present invention provides an exposure apparatus and an exposure method. The method comprises: utilizing an exposure light source to provide light rays to the photo-resist layer, wherein the light rays pass through the mask and the transparent substrate to reach the photo-resist layer; and utilizing a reflective plate to reflect the light rays passing through the transparent substrate and the photo-resist layer back to the photo-resist layer. The present invention can reduce a line space of a pattern of the photo-resist layer.

A liquid crystal display device is disclosed, comprising a first substrate, a second substrate and a liquid crystal layer. The first substrate comprises gate lines and a first transparent electrode while the second substrate is provided with a second transparent electrode. Relative to the first substrate, the inner side of the second substrate is separated into a first zone and a second zone. The first zone is locations on the second substrate to which the gate lines correspond, and the second zone is located aside to the locations on the second substrate that correspond to the gate lines. The second transparent electrode is disposed in the second zone. The liquid crystal display device of the present invention is capable of reducing parasitic capacitance of gate lines preferably, enabling the signal delay to subside in the gate lines.

Liquid crystal display device

The present invention discloses an ESD protection device of an LCD display. The LCD display includes a plurality of scan lines and a plurality of data lines, the scan lines and the data lines are crossed. The ESD protection device includes a discharging extension part, positioned at ends of the scan lines and the data lines, wherein a width of the discharging extension part is larger than line widths of the scan lines or the data lines; and an electro-static conducting part, positioned in peripheral of the discharging extension part, wherein the electro-static conducting part is close to the discharging extension part without touching the discharging extension part, and the electro-static conducting part is coupled to a common conducting layer to release electro-static charges on the scan lines and data lines via the common conducting layer. The present invention can enormously reduce the ESD damages on the pixel areas.

ESD protection device of LCD display

The present invention provides methods for manufacturing a thin film transistor (TFT) array substrate and a display panel. The method for manufacturing the TFT array substrate comprises the following steps: forming a plurality of gate electrodes, a gate insulating layer, a semiconductor layer, an ohmic contact layer, an electrode layer and a photo-resist layer on a transparent substrate in sequence; using a multi tone mask to pattern the photo-resist layer; forming a plurality of source electrodes and a plurality of drain electrodes at both sides of the channels, respectively; heating the photo-resist layer; etching the semiconductor layer; removing the photo-resist layer; forming a passivation layer on the channels, the source electrodes and the drain electrodes; and forming a pixel electrode layer on the passivation layer. The present invention can reduce an amount of the required masks in the fabrication process, and only one wet etching is required to etch the metal material on the TFT array substrate.

Methods for manufacturing thin film transistor array substrate and display panel

The present invention provides methods for manufacturing a thin film transistor (TFT) array substrate and a display panel. The method for manufacturing the TFT array substrate comprises the following steps: forming a plurality of gate electrodes, a gate insulating layer, a semiconductor layer, an ohmic contact layer, an electrode layer and a first photo-resist layer on a transparent substrate in sequence; patterning the first photo-resist layer; etching the ohmic contact layer and the electrode layer; coating a second photo-resist layer on the patterned first photo-resist layer and in the channels; removing the second photo-resist layer on the patterned first photo-resist layer and to allow the second photo-resist layer in the channels to remain therein; etching the semiconductor layer; removing the patterned first photo-resist layer and the second photo-resist layer; forming a passivation layer on the channels, the source electrodes and the drain electrodes; and forming a pixel electrode layer on the passivation layer. The present invention can reduce an amount of the required masks in the fabrication process, and only one wet etching is required to etch the metal material on the TFT array substrate.

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Shenzhen, China

Jehao Hsu