Hewlett-Packard Company

Hewlett-Packard Development Company, L.p.

Jeffry D Yetter

Terrel L Morris

David Martin Fenwick

Duane A Wegher

Richard John Luebs

Robert H Miller, Jr

Dacheng Zhou

Samuel D Naffziger

Daniel Alan Berkram

Glenn T Colon-Bonet

Robert James Martin

Paul L Perez

Russell W Mason

Ricahrd John Luebs

An array of light beam emitter sections comprises: a substrate having a surface divided into an array of sections; and a grouping of light emitters disposed at each surface section and configured to emit light beams at different emission angles with respect to the surface. Also disclosed is apparatus for establishing optical communication channels between the array of light beam emitter sections and an array of light detectors. Further disclosed is a method of establishing optical communication channels between the array of light emitter sections and the array of light detectors by mapping at least one light emitter of each grouping with a light detector of the detector array to establish optical communication channels between the arrays based on the mappings.

Apparatus and method of establishing optical communication channels between a steerable array of laser emitters and an array of optical detectors

A bias voltage generation circuit is provided which includes a voltage-to-current translation circuit configured to generate a first current that is positively related to a first voltage. A current mirror circuit is configured to generate a first bias voltage that is negatively related to the first current. The current mirror circuit also generates a second current that is positively related to the first current. Also employed is a current-to-voltage translation circuit configured to generate a second bias voltage that is positively related to the second current.

Circuit and method for bias voltage generation

An AC coupling circuit is disclosed herein. An embodiment of the circuit comprises a first differential input and a second differential input. A first resistor is connected between the first differential input and the second differential input. A first capacitor is connected between the first differential input and a first differential output. A second capacitor is connected between the second differential input and a second differential output. A second resistor is connected between the first differential output and a node. A third resistor is connected between the second differential output and the node. A first potential is applied to the node.

AC coupling circuit

An array of light beam emitter sections comprises: a substrate having a surface divided into an array of sections; and a grouping of light emitters disposed at each surface section and configured to emit light beams at different emission angles with respect to the surface. Also disclosed is apparatus for establishing optical communication channels between the array of light beam emitter sections and an array of light detectors. The apparatus comprises a controller coupled to the arrays of emitter sections and detectors for mapping at least one light emitter of each grouping with a light detector of the detector array to establish optical communication channels between the arrays based on the mappings. Further disclosed is a method of establishing optical communication channels between the array of light emitter sections and array of light detectors by mapping at least one light emitter of each grouping with a light detector of the detector array to establish optical communication channels between the arrays based on the mappings.

A system for configuring fiber optic communication channels between arrays of emitters and detectors comprises: an array of light emitters; an array of light detectors; a bundle of optical fibers disposed between the arrays of light emitters and light detectors for conducting light from the light emitters to the light detectors, wherein the number of optical fibers in the bundle is greater than the number of light emitters in the array and wherein an area cross-section of the bundle of optical fibers overlaps the array of light emitters and the array of light detectors; and logic for mapping at least one emitter to at least one detector to establish at least one optical fiber communication channel between the array of light emitters and the array of light detectors. The system is further operative to monitor data communication over the at least one fiber optic communication channel and to reconfigure the mapping based on the monitored data communications thereof. A counterpart method of configuring fiber optic communication channels between arrays of emitters and detectors is also disclosed.

System and method of configuring fiber optic communication channels between arrays of emitters and detectors

A system for self-configuring optical communication channels between arrays of emitters and detectors comprises: an array of light emitters; an array of light detectors roughly aligned with the array of light emitters; and self-configuration logic for controlling the light emitters of the emitter array to transmit optical data to the array of light detectors and for monitoring received optical data of the light detectors of the detector array to establish light emitter/detector optical channels between the arrays of light emitters and light detectors based on optical data transmission error rates. In addition, a method of self-configuring optical communication channels between arrays of emitters and detectors comprises the steps of: roughly aligning an array of light emitters to an array of light detectors; controlling the light emitters of the emitter array to transmit optical data to the array of light detectors; and monitoring received optical data of the light detectors of the detector array to establish light emitter/detector optical channels between the arrays of light emitters and light detectors based on optical data transmission error rates.

System and method of self-configuring optical communication channels between arrays of emitters and detectors

A system for configuring fiber optic communication channels between arrays of emitters and detectors comprises: an array of light emitters; an array of light detectors; a bundle of optical fibers disposed between the arrays of light emitters and light detectors for conducting light from the light emitters to the light detectors, wherein a diameter of each optical fiber in the bundle is greater than a diameter of light emitted from each light emitter in the array, and wherein an area cross-section of the bundle of optical fibers overlaps the array of light emitters and the array of light detectors; and logic for mapping at least one emitter to at least one detector to establish at least one fiber optic communication channel between the array of light emitters and the array of light detectors. A counterpart method is also disclosed.

Apparatus for connecting an interconnecting cable between first and second printed circuit (PC) boards comprises: a base member disposed on a side of the first PC board for fixedly attaching one end of the interconnecting cable to the first PC board; a first connector attached to the other end of the interconnecting cable; a second connector disposed on a side of the second PC board; and a spring member attached to the base member for supporting the first connector away from the side of the first PC board, the spring member operative to force the first connector against the side of the second PC board to cause slidable engagement of the first and second connectors when one of the first and second PC boards is slid past the other of the first and second PC boards. Apparatus and method of providing optical connection between a first optical array electrically coupled to a first printed circuit (PC) board and a second optical array electrically coupled to a second PC board for providing optical communication between the first and second optical arrays are also disclosed.

Apparatus and method of providing an optical connection between PC boards for optical communication

A circuit for reducing capacitive coupling between a culprit and a victim signal line is provided which comprises two inverters, a n-channel FET connected as a capacitor, and a p-channel FET connected as a capacitor. The input of both inverters are connected to the culprit line. The first inverter is designed to respond to high-to-low transition on the culprit line more rapidly than a low-to-high transition. The output of the first inverter is connected to the drain and source of the n-channel FET. The gate of the n-channel FET is connected to the victim line. The second inverter is designed to respond to low-to-high transition on the culprit line more rapidly than a high-to-low transition. The output of the second inverter is connected to the drain and source of the p-channel FET. The gate of the p-channel FET is connected to the victim line.

Coupling charge compensation device for VLSI circuits

A register selection system increases a speed for selection of memory registers when selection is based upon a constant K defined by a sum of two numbers. The register selection system includes a specialized predecoder interconnected with a specialized decode array. The predecoder has first and second address inputs. The predecoder is configured to process first and second address values each of width n on the first and second address inputs respectively in order to produce first, second, third, and fourth predecoded values of width n on respective predecoder outputs. The first, second, third, and fourth predecoded values have respective widths of n+1, n, n, n-1. The decode array, which is connected to the predecoder outputs, is configured to receive the predecoded values. The decode array has 2.sup.n+1 register select outputs corresponding respectively with registers. The decode array is configured to assert one of the register select outputs, while deasserting a remainder of the register select outputs, based upon the predecoded values. As a result, a determination is made as to when the two numbers equal the constant K without performing a summing operation and a carry propagation associated with the summing operation. Moreover, a selection of the one register is accomplished based upon the determination.

Register selection system and method

The present invention relates to computer systems utilizing a TLB with variable sized pages. This invention detects conflicts between address tags stored in the TLB and a prospective address tag. In particular this invention detects conflicts when the prospective tag represents an address space that overlaps, wholly includes or is included in the address space represented by a tag stored in the TLB. By detecting tag conflicts utilizing hardware, a tremendous performance gain is achieved over systems utilizing prior art software systems.

Method and apparatus to eliminate redundant mapping in a TLB utilizing

Disclosed herein are methods and apparatus for performing magnitude comparisons within a shift-merge unit (SMU). A programmable or partially programmable Manchester carry chain is used to perform each comparison. The Manchester carry chains are programmed using the bits of mask markers and are constructed so as to make a comparison with respect to a given mask condition and position marker which are constants. An implementation in dual rail dynamic CMOS logic avoids the necessity of input inversions, and allows construction of more compact Manchester carry chain circuitry. The size of an SMU will therefore be determined by mask marker routings rather than transistor count. When shorted, opened, and/or redundant transistors, and/or transistors programmed with constants are optimized out of constructed Manchester carry chains, the mask marker bits of a dual rail SMU will have equal fanouts, thereby preventing clock skew. Manchester carry chains may be broken into modular components which may be stepped a number of times to create a 2.sup.N bit SMU. Breaking carry chains into modular components also allows the creation of a single mask, or several smaller masks, within a single SMU. This is an important factor in handling multimedia data which comprises smaller word lengths than instruction data.

Parallel magnitude comparison using manchester carry chains

Clocking systems and methods of the present invention use two or more different clock signals for respective groups or stages of self-timed dynamic (or mousetrap) logic gates. Each clock signal defines a precharging time interval and an evaluation time interval for its respective group or stage of self-timed dynamic logic gates. Using the two or more different clock signals, pipelining of the groups or stages of the self-timed dynamic logic gates can be performed.

Clocking systems and methods for pipelined self-timed dynamic logic

Vector logic is implemented by pipelining logic stages comprised of dynamic mousetrap logic gates. A novel pipeline latch is associated with each logic stage of the pipeline. Each pipeline latch has a latch reset mechanism, an input trigger mechanism, a disabling mechanism, a flip-flop mechanism, an output gating mechanism, and a latch enable pull-up mechanism. Moreover, the logic stages are alternately clocked. While the even numbered stages are receiving a high clock signal for instigating propagation, the odd numbered stages are receiving a low clock signal for instigating precharging, and vice versa. The high and low clock times for each stage is substantially equivalent. Due to inherent manufacturing inequalities, clock asymmetry results. An advantaged and disadvantaged phase arises. Because of the novel latch and associated method, pipeline stages operating in the disadvantaged phase can steal time from those operating in the advantaged phase. Further, no minimum clock frequency is required.

Universal pipeline latch for mousetrap logic circuits

A dynamic mousetrap logic gate implements a self-timed monotonic logic progression via a novel vector logic method. In the vector logic method, a vector logic variable is defined by a plurality of vector components situated on respective logic paths. Boolean as well as non-Boolean variables can be represented. Further, timing information is encoded in the vector logic variable itself by defining the vector logic variable as invalid when all the vector components currently exhibit a logic low and by defining the vector logic variable as valid when a subset of the vector components exhibits a logic high. With a plurality of valid vector logic states, subsets defining valid vector logic states are nonoverlapping. The mousetrap logic gate comprises a plurality of gate components in parallel, corresponding with each output vector component. Each gate component has an arming mechanism, a ladder logic, and an inverting buffer mechanism. The ladder logic performs logic functions on one or more input vectors and provides the result to the inverting buffer mechanism. The arming mechanism periodically precharges the inverting buffer input to drive the gate component output to a logic low until the inverting buffer mechanism is triggered by the ladder logic.

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Loveland, CO, United States of America

Jeffry D Yetter