Cypress Semiconductor Corporation

Freescale Semiconductor,inc.

Intel Corporation

Jeffrey William Waldrip

Stephen Myles Prather

Alexander Hoefler

Jeffery Scott Hunt

Matthew S Berzins

Satish C Saripella

Ajay Srikrishna

Sudhaker Reddy Anumula

Prashant U Kenkare

Yongping Fan

Muthukumar Nagarajan

Charles A Cornell

Jing Li

In some embodiments, provided are AFC circuits and methods for calibrating a second setting of an oscillator while a first setting is controlled by a temperature compensated control.

Temperature compensated PLL calibration

A circuit has a master latch having an input for receiving an input data signal, and an output. A slave latch has a first input coupled to the output of the master latch, and an output for providing an output data signal. A non-volatile storage element stores a predetermined value. The non-volatile storage element has an output coupled to the first input of the slave latch. The output data signal corresponds to one of either the input data signal or the predetermined value stored by the non-volatile storage element in response to a control signal.

Scannable flip-flop with non-volatile storage element and method

Output driver circuits and related methods. In one example, the output driver circuit includes a translator for converting the single ended data input signal into a pair of signals; a set of output transistors selectively controlled by the pair of signals; a cascode current source for providing a substantially constant current to the set of output transistors when the output transistors are active; and a dump path in parallel with the set of output transistors. A circuit portion for pre-charging the pair of signals to a pre-charged voltage between VCC and ground may also be provided.

Circuit and method for rapid power up of a differential output driver

A device having an OTP memory is disclosed. A program state of the OTP device is stored at a fuse that is connected in series between a first node and a latch. During a program mode, the first node is electrically connected to a program voltage. During a read mode, the first node is electrically connected to ground, whereby a first divided voltage is generated at a first node of the latch.

Programmable cell

A circuit according to some embodiments of the invention includes a first differential to single ended translator having a first output, a second differential to single ended translator having a second output, and a latch coupled to the first output and the second output, where the latch is configured to select the slower of the first output and the second output.

Method and circuit for translating a differential signal to complementary CMOS levels

An apparatus comprising one or more input/output circuits that may be configured as (i) high voltage tolerant in response to a first state of a control input and (ii) a clamp to a power supply voltage in response to a second state of said control input.

Configurable PCI clamp or high voltage tolerant I/O circuit

A circuit that may be configured to provide a first well bias voltage to the output buffer when the output buffer is in a first mode and to provide a second well bias voltage to the output buffer when the output buffer is in a second mode. The first well bias voltage and the second well bias voltage may be used to maintain a reverse bias in diffusion wells used for electrical isolation of transistors.

Control signal generator for an overvoltage-tolerant interface circuit on a low voltage process

A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) an enable signal and (ii) a detect signal.

Method, architecture and circuit for writing to and reading from a

A circuit and method comprising a memory, a first latch, a second latch and a control circuit. The memory may be configured to write information in response to (i) an input data signal and (ii) an address signal. The first latch may be configured to hold the address in response to a control signal. The second latch may be configured to hold the data input signal in response to the control signal. The control circuit may be configured to present the control signal in response to (i) a detect signal and (ii) a transition of the address signal.

Growing community of inventors

Austin, TX, United States of America

Jeffrey William Waldrip