Applied Micro Circuits Corporation

Jeffrey W Spires

Ravi Subrahmanyan

A timeshared data tributary mapping system and method are provided for mapping information into Synchronous Payload Envelopes (SPEs). The method buffers data from a plurality of tributaries and stores current buffer-fill information at a rate of about one tributary per Fsys clock cycle. An accumulation of buffer-fill information for the plurality of tributaries is updated with current buffer-fill information every Fsys clock cycle. The accumulation of buffer-fill information for the plurality of tributaries is sampled at a sample rate frequency (Fsample), where Fsample&#x3c;Fsys. The sampled buffer-fill information is used to calculate a data rate control word for each of the plurality of tributaries, and stuff bit opportunities are serially calculated responsive to the control word. The rate of data being mapped into outgoing tributaries is regulated, and the outgoing mapped tributaries are combined in a SPE.

Timeshared jitter attenuator in multi-channel mapping applications

A system and modulation method are provided for reducing jitter in the mapping of information into Synchronous Payload Envelopes (SPEs), in a data tributary mapping system. The method comprises buffering data from a plurality of tributaries, and generating buffer-fill information responsive to the buffered data being written and read. The buffer-fill information is filtered, producing rate control information. The rate control information is modulated, and the modulated rate control information is used in controlling the mapping of buffered tributaries into a SPE. The rate control information can be modulated with periodic signals, such as a sine or square wave, and pseudorandom signals with an average value of about zero.

Modulated jitter attenuation filter

The present invention is for an apparatus that receives input data at a non-uniform first data rate carried by a system clock, and provides output data at a substantially uniform second data rate that is nominally equal to the first data rate and is also carried by the system clock. The system clock is faster than the first or second data rates and accordingly, a write enable signal controls the input data that is written into a saturating elastic store and a read enable signal controls the reading and output of data from the saturating elastic store. The saturating elastic store includes a plurality of storage locations and provides a storage fill level indicative of the amount of storage locations currently holding data. A digital filter receives the storage fill level and filters the storage fill level to provide a control word to a digitally controlled read enable signal generator. The digitally controlled read enable signal generator provides a read enable signal that is nominally the second data rate and that can be varied about the nominal second data rate in response to the control word. The digitally controlled read enable signal generator is able to vary the read enable signal rate by providing a plurality of stuff bit opportunities interspersed between the read enable signals. Some of these stuff bit opportunities are filled to set the read enable signal rate at the nominal second data rate value. By filling or not filling the stuff bit opportunities, the read enable signal rate can be adjusted over a narrow band of frequencies.

Jitter and wander reduction apparatus

An apparatus for reducing the effects of pointer adjustments, wander, and jitter during desynchronization of a non-uniformly gapped data stream from a payload of a synchronized signal is disclosed. The apparatus utilizes a combination of two pointer adjustment signals embedded in the synchronized signal to determine a bit leak rate of bits from an elastic store following a pointer adjustment event such that the elastic store provides as an output a more-uniformly-distributed-gapped data stream.

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Salt Lake City, UT, United States of America

Jeffrey W Spires