International Business Machines Corporation

Globalfoundries Inc.

Other

Advanced Micro Devices Corporation

Elpis Technologies Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Jeffrey W Sleight

Josephine B Chang

Isaac Lauer

Leland Chang

Chung-Hsun Lin

Sarunya Bangsaruntip

Michael A Guillorn

Guy M Cohen

Amlan Majumdar

Paul S Chang

Shreesh Narasimha

Renee Tong Mo

Gen Pei Lauer

Vijay Narayanan

Zhibin Ren

Karthik Balakrishnan

Martin Michael Frank

Dinkar Virendra Singh

Anirban Basu

Tenko Yamashita

Andres Bryant

Anthony I Chou

Alexander Reznicek

Toshiharu Furukawa

Unoh Kwon

Siddarth A Krishnan

Steven John Koester

Shih-Hsien Lo

Edward J Nowak

Wilfried Haensch

John Michael Hergenrother

Bruce Bennett Doris

Anthony K Stamper

Brent A Anderson

Dureseti Chidambarrao

Terence B Hook

Michael Patrick Chudzik

Arvind Kumar

Conal Eugene Murray

Vamsi Krishna Paruchuri

Min Yang

William K Henson

Sebastian Ulrich Engelmann

Anda C Mocuta

Ryan M Martin

Ghavam G Shahidi

Stephen W Bedell

Ying Di Zhang

Kern Rim

Omer H Dokumaci

Tymon Barwicz

Oki Gunawan

Meikei Ieong

Jin Cai

Wesley Charles Natzle

Xinhui Wang

Brian L Ji

David James Frank

Kathryn Wilder Guarini

Patrick Ronald Varekamp

Lidija Sekaric

Hung H Tran

Szu-Lin Cheng

Daniel K Tekleab

Pouya Hashemi

John J Ellis-Monaghan

Balasubramanian Pranatharthiharan

Kerry Bernstein

Dominic Joseph Schepis

Kenneth Parker Rodbell

Ravikumar Ramachandran

John Joseph Pekarik

Pranita Kerber

Hiroyuki Miyazoe

Markus Brink

Richard Quimby Williams

Norman Jay Rohrer

Ching-Te Kent Chuang

Robert L Sandstrom

Philip A Fisher

Siyuranga O Koswatta

Junedong Lee

Koushik Kumar Das

Adam M Pyzyna

Charlotte DeWan Adams

Ryan T Gordon

Gen Pei

Akihisa Sekiguchi

Anthony I-Chih Chou

Suk Hoon Ku

James T Kelliher

Isaac Laurer

Issac Lauer

Renee T Mo

A field effect transistor (FET) includes a substrate; a channel material located on the substrate, the channel material comprising one of graphene or a nanostructure; a gate located on a first portion of the channel material; and a contact aligned to the gate, the contact comprising one of a metal silicide, a metal carbide, and a metal, the contact being located over a source region and a drain region of the FET, the source region and the drain region comprising a second portion of the channel material.

Graphene/nanostructure FET with self-aligned contact and gate

Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a superconducting circuit provided on an encapsulated vacuum cavity are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise a superconducting circuit provided on the encapsulated vacuum cavity.

Superconducting circuit provided on an encapsulated vacuum cavity

Devices, systems, methods, and/or computer-implemented methods that can facilitate a qubit device comprising a vacuum encapsulated Josephson junction are provided. According to an embodiment, a device can comprise a substrate having an encapsulated vacuum cavity provided on the substrate. The device can further comprise one or more superconducting components of a superconducting circuit provided inside the encapsulated vacuum cavity.

Vacuum encapsulated Josephson junction

Techniques regarding qubit structures comprising ion implanted Josephson junctions are provided. For example, one or more embodiments described herein can comprise an apparatus that can include a strip of superconducting material coupling a first superconducting electrode and a second superconducting electrode. The strip of superconducting material can have a first region comprising an ion implant and a second region that is free from the ion implant.

Qubits with ion implant Josephson junctions

In one aspect, a method of forming a local interconnect structure includes the steps of: forming a BOX SOI wafer having a fully depleted seed layer between a first BOX layer and a second BOX layer, and an active layer over the second BOX layer; forming at least one STI region in the active layer having an STI oxide; forming at least one trench that extends through the STI oxide and the second BOX layer down to the seed layer, wherein the trench has a footprint and a location such that a portion of the STI oxide remains lining sidewalls of the trench; and growing an epitaxial material in the trench using the seed layer as a template for the growth, wherein the epitaxial material is doped and serves as the local interconnect structure which is buried in the double BOX SOI wafer.

Techniques for creating a local interconnect using a SOI wafer

At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.

Strained semiconductor nanowire

Techniques for forming dual III-V semiconductor channel materials to enable fabrication of different device types on the same chip/wafer are provided. In one aspect, a method of forming dual III-V semiconductor channel materials on a wafer includes the steps of: providing a wafer having a first III-V semiconductor layer on an oxide; forming a second III-V semiconductor layer on top of the first III-V semiconductor layer, wherein the second III-V semiconductor layer comprises a different material with an electron affinity that is less than an electron affinity of the first III-V semiconductor layer; converting the first III-V semiconductor layer in at least one second active area to an insulator using ion implantation; and removing the second III-V semiconductor layer from at least one first active area selective to the first III-V semiconductor layer.

Hybrid III-V technology to support multiple supply voltages and off state currents on same chip

A silicon-on-insulator substrate which includes a semiconductor substrate, a buried oxide layer, and a semiconductor layer is provided. A hard mask layer is formed over a first region of the silicon-on-insulator substrate. A first silicon-germanium layer is epitaxially grown on the semiconductor layer within a second region of the silicon-on-insulator substrate. The second region is at least a portion of the semiconductor layer not covered by the hard mask layer. A thermal annealing process is performed, such that germanium atoms from the first silicon-germanium layer are migrated to the portion of the semiconductor layer to form a second silicon-germanium layer. The hard mask layer is removed. A layer of semiconductor material is epitaxially grown on top of the semiconductor layer and the second silicon-germanium layer, where the layer of semiconductor material composed of the same material as semiconductor layer.

Implementing a hybrid finFET device and nanowire device utilizing selective SGOI

A nanowire device includes a first component formed on a substrate and a second component disposed apart from the first component on the substrate. A nanowire is configured to connect the first component to the second component. An anchor pad is formed along a span of the nanowire and configured to support the nanowire along the span to prevent sagging.

Support for long channel length nanowire transistors

Various embodiments are directed toward a circuit configured to act as a Josephson junction. The circuit includes: a junction stack on a substrate, the junction stack including a portion of a first superconductor electrode, with an interface layer on a top side of the first superconductor electrode and configured to act as a tunneling barrier for the junction stack. The circuit may also comprise a first portion of a second superconductor electrode on top of the interface layer. A spacer may separate the portion of the first superconductor electrode in the junction stack from a second portion of the second superconductor electrode outside the junction stack where the second superconductor electrode overlays the first superconductor electrode, the second portion of the second superconductor electrode contacting the substrate on at least one side of the spacer.

Josephson junction with spacer

A nanowire field effect transistor (FET) device includes a first source/drain region and a second source/drain region. Each of the first and second source/drain regions are formed on an upper surface of a bulk semiconductor substrate. A gate region is interposed between the first and second source/drain regions, and directly on the upper surface of the bulk semiconductor substrate. A plurality of nanowires are formed only in the gate region. The nanowires are suspended above the semiconductor substrate and define gate channels of the nanowire FET device. A gate structure includes a gate electrode formed in the gate region such that the gate electrode contacts an entire surface of each nanowire.

Wire-last gate-all-around nanowire FET

After forming a buried nanowire segment surrounded by a gate structure located on a substrate, an epitaxial source region is grown on a first end of the buried nanowire segment while covering a second end of the buried nanowire segment and the gate structure followed by growing an epitaxial drain region on the second end of the buried nanowire segment while covering the epitaxial source region and the gate structure. The epitaxial source region includes a first semiconductor material and dopants of a first conductivity type, while the epitaxial drain region includes a first semiconductor material different from the first semiconductor material and dopants of a second conductivity type opposite the first conductivity type.

Expitaxially regrown heterostructure nanowire lateral tunnel field effect transistor

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Ridgefield, CT, United States of America

Jeffrey W Sleight