Sandisk Corporation

Sandisk Technologies Inc.

Koninklijke Philips Corporation N.v.

Kabushiki Kaisha Toshiba

Philips Semiconductor, Inc.

Jeffrey W Lutze

Yan Li

Jun Wan

Yingda Dong

Deepanshu Dutta

Jian Feng Chen

Nima Mokhlesi

Dana Lee

Masaaki Higashitani

Gerrit Jan Hemink

Yupin K Fong

Tuan Duc Pham

George Matamis

Henry Chien

Teruhiko Kamei

Dat Tran

Kiran Ponnuru

Tomoharu Tanaka

Ken Oowada

Changyuan Chen

Grishma Shah

Hua-Ling Cynthia Hsu

Chan-Sui Pang

Hidetaka Horiuchi

Daniel C Guterman

Henry Chin

Jian Chen

Siu Lung Chan

Shih-Chung Lee

Geoffrey Steven Gongwer

Loc Tu

Kazunori Kanebako

Alex Mak

Emmanuel De Muizon

Man Lung Mui

Shinji Sato

Toru Ishigaki

A set of non-volatile storage elements are subjected to a programming process in order to store data. During the programming process, one or more verification operations are performed to determine whether the non-volatile storage elements have reached their target. Non-volatile storage elements being programmed to a first set of one or more targets are verified to determine whether they have reached their target and are locked out of further programming if it is determined that they have reached their target. Non-volatile storage elements being programmed to the second set of one or more targets are tested to determine the number of fast programming bits. When the number of fast bits for a particular target is greater than a threshold, then programming stops for the non-volatile storage elements being programmed to the particular target.

Programming non-volatile storage with fast bit detection and verify skip

A non-volatile storage system performs programming for a plurality of non-volatile storage elements and selectively performs re-erasing of at least a subset of the non-volatile storage elements that were supposed to remain erased, without intentionally erasing programmed data.

Programming and selectively erasing non-volatile storage

In a programming operation, selected storage elements on a selected word line are programmed while unselected storage elements on the selected word line are inhibited from programming by channel boosting. To provide a sufficient but not excessive level of boosting, the amount of boosting can be set based on a data state of the unselected storage element. A greater amount of boosting can be provided for a lower data state which represents a lower threshold voltage and hence is more vulnerable to program disturb. A common boosting scheme can be used for groups of multiple data states. The amount of boosting can be set by adjusting the timing and magnitude of voltages used for a channel pre-charge operation and for pass voltages which are applied to word lines. In one approach, stepped pass voltages on unselected word lines can be used to adjust boosting for channels with selected data states.

Data state-dependent channel boosting to reduce channel-to-floating gate coupling in memory

In a non-volatile memory system, a programming operation applies programming pulses to a target word line, determines when a specified number of the non-volatile storage elements reach a defined verify level, and counts a specified number of the programming pulses after the specified number of the non-volatile storage elements reach the defined verify level. Upon completion of the counting, faster-programming storage elements are distinguished from slower-programming storage elements. Programming continues for of at least some of the faster-programming non-volatile storage elements, with an associated programming speed-based slow down measure imposed thereon, and for at least some of the slower-programming non-volatile storage elements without imposing a programming speed-based slow down measure.

Natural threshold voltage distribution compaction in non-volatile memory

A plurality of non-volatile storage elements on a common active layer are offset from neighbor non-volatile storage elements. This offsetting of non-volatile storage elements helps reduce interference from neighbor non-volatile storage elements. A method of manufacture is also described for fabricating the offset non-volatile storage elements.

Offset non-volatile storage

Dynamically determining read levels on chip (e.g., memory die) is disclosed herein. One method comprises reading a group of non-volatile storage elements on a memory die at a first set of read levels. Results of the two most recent of the read levels are stored on the memory die. A count of how many of the non-volatile storage elements in the group showed a different result between the reads for the two most recent read levels is determined. The determining is performed on the memory die using the results stored on the memory die. A dynamic read level is determined for distinguishing between a first pair of adjacent data states of the plurality of data states based on the read level when the count reaches a pre-determined criterion. Note that the read level may be dynamically determined on the memory die.

On chip dynamic read for non-volatile storage

A technique for erasing a non-volatile memory applies a p-well voltage to a substrate and drives select gate voltages to accurately control the select gate voltage to improve write-erase endurance. Source and drain side select gates of a NAND string are driven at levels to optimize endurance. In one approach, the select gates are driven at specific levels throughout an erase operation, in concert with the p-well voltage.

Controlling select gate voltage during erase to improve endurance in non volatile memory

In a non-volatile memory system, a multi-phase programming operation is performed. In one phase, faster-programming storage elements have a higher bit line bias (Vbl) than slower-programming storage elements. In a next phase, the faster- and slower-programming storage elements have a lower Vbl. Further, a drain-side select gate voltage (Vsgd) can be adjusted in the different programming phases to accommodate the different Vbl levels. A higher Vsgd can be used in the one phase when Vbl is higher to avoid unnecessary stress on the SGD transistor and reduce power consumption. Vsgd can be reduced in the next phase when the lower Vbl is used. The higher Vbl is a slowdown measure which can be applied when the Vth of a storage element is between lower and upper verify levels of target data states, or throughout a programming phase.

A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. First, second and third sets of non-volatile storage elements are programmed in separate sequences, one after another, so that all program-verify operations occur for the first set, then for the second set, and then for the third set. Each non-volatile storage element in a set is separated from the next closest non-volatile storage element in the set at least two other non-volatile storage elements in the set.

Sequential programming of sets of non-volatile elements to improve boost voltage clamping

A non-volatile storage system reduces program disturb in a set of non-volatile storage elements by programming using selected bit line patterns which increase the clamped boosting potential of an inhibited channel to avoid program disturb. Alternate pairs of adjacent bit lines are grouped into first and second sets. Non-volatile storage elements of the first set of pairs are subject to program pulses and verify operations in each of a first number of iterations, after which non-volatile storage elements of the second set of pairs is subject to program pulses and verify operations in each of a second number of iterations.

Pair bit line programming to improve boost voltage clamping

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San Jose, CA, United States of America

Jeffrey W Lutze