Motorola Corporation

Madrone Solutions, Inc.

Other

Jeffrey Van Myers

Michael L Longwell

William Daune Atwell

Shrirang Nikanth Jambhekar

James R Huffman

Russell L Collins

Ronald D Cruickshank

William C Moyer

Stuart D Green

Jonathan M Crain

Carl A Perry

Marcus L Yax

Scott G Brown

Noel R Strader, Ii

Lawrence Seligman

Nathan Elnathan

A FireNet security system in which trustworthy networks, called BlackNets, each comprising One (1) or more client computers, are protected by FireBreaks against attacks from untrustworthy networks, called RedNets. All incoming transactions from the RedNet are examined by the FireBreak to determine if they violate any of a plurality of protection rules stored in a local protection rules database. Any transaction found to be in violation is discarded. Valid transactions are forwarded to the BlackNet. If an otherwise valid transaction is found to be suspicious, the FireBreak will forward to a FireNet Server relevant information relating to that transaction. If the FireNet Server verifies that the transaction is indeed part of an attack, the FireNet Server will create new protection rules suitable to defend against the newly identified source or strategy of attack. Periodically, all FireBreaks in the FireNet system will transfer, directly or indirectly, all new rules.

Improving security of data communications networks

A Random Access Error Detection and Correction unit (RAEDAC) that incorporates a bit-wise error detection and correction unit (BEDAC) in a memory system. In one embodiment, a word-wise error detection and correction unit (WEDAC) operates in coordination with a BEDAC that performs a bit-wise parity calculation. In another embodiment, a WEDAC operates in coordination with a full bit-wise BEDAC that calculates bit-wise check bits. The RAEDAC may be applied to create a multi-dimensional EDAC where, for example, the memory is partitioned into a stack of planes, and a stack-wise error detection and correction unit (SEDAC) is implemented.

Method and apparatus for error detection and correction

An apparatus for operating a dynamic memory ( ) in a sleep mode. The apparatus writes a predetermined background value to at least a background portion of the memory, and then ceases to refresh the background portion. The background value corresponds to the conductivity type of the memory cell, where N-channel devices have a low value and P-channel devices have a high value. After return from sleep mode, the voltage reference is not impacted by the residual charge in the memory cells. According to one embodiment, a refresh controller ( ) accesses a look up table ( ) to store data indicating the status of memory cells. Prescaling may then adjust the period and duty cycle of the refresh cycle in response to the inactive wordlines via a unit, such as prescaler ( ). In one embodiment, the background value is written to the inactive memory cell ( ) via sense amplifier killer circuitry ( ).

Apparatus for operating an integrated circuit having a sleep mode

A method for tracking errors in a memory system by detecting an error in a bit of a word accessed in the memory and maintaining an error history comprising a record of each of the detected errors. The error history information may be used to configure the memory, such as to add redundancy; or may be used to adjust operating parameters of the memory, such as the periodicity of refresh and/or scrub operations; or may be used to trigger a sensing operation of other parameters in an application system. In one embodiment, a counter increments each time an error is detected and decrements when no error is detected, thereby tracking error patterns.

Method for apparatus for tracking errors in a memory system

A plurality of memory tiles ( ) are arranged to form a tiled memory array ( ) in an integrated circuit device ( ). In accordance with the present invention, each of the memory tiles ( ) in the tiled memory array ( ) has charge source circuitry ( ) to provide the sufficient reference voltages for proper operation of the memory tile ( ). In addition, each memory tile ( ) may include local error detection and correction circuitry ( ). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry ( &Prime;).

Memory tile for use in a tiled memory

A plurality of memory tiles ( ) are arranged to form a tiled memory array ( ) in an integrated circuit device ( ). In accordance with the present invention, each of the memory tiles ( ) in the tiled memory array ( ) has charge source circuitry ( ) to provided the sufficient reference voltages for proper operation of the memory tile ( ). In addition, each memory tile ( ) may include local error detection and correction circuitry ( b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry ( 41 ).

Tiled memory and memory tile for use therein

A method for operating a dynamic memory ( ) in a sleep mode. The method writes a predetermined background value to at least a background portion of the memory, and then ceases to refresh the background portion. The background value corresponds to the conductivity type of the memory cell, where N-channel devices have a low value and P-channel devices have a high value. After return from sleep mode, the voltage reference is not impacted by the residual charge in the memory cells. According to one embodiment, a refresh controller ( ) accesses a look up table ( ) to store data indicating the status of memory cells. Prescaling may then adjust the period and duty cycle of the refresh cycle in response to the inactive wordlines via a unit, such as prescaler ( ). In one embodiment, the background value is written to the inactive memory cell ( ) via sense amplifier killer circuitry ( ).

Method for operating an integrated circuit having a sleep mode

A plurality of memory tiles (,) are arranged to form a tiled memory array (,) in an integrated circuit device (,). In accordance with the present invention, each of the memory tiles (,) in the tiled memory array (,) has charge source circuitry (,) to provide the sufficient reference voltages for proper operation of the memory tile (,). In addition, each memory tile (,) may include local error detection and correction circuitry (,). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (,&Prime;).

Method for designing a tiled memory

A plurality of memory tiles (22) are arranged to form a tiled memory array (12) in an integrated circuit device (400). In accordance with the present invention, each of the memory tiles (22) in the tiled memory array (12) has charge source circuitry (24) to provide the sufficient reference voltages for proper operation of the memory tile (22). In addition, each memory tile (22) may include local error detection and correction circuitry (36b). To facilitate reliable operation, each memory tile may also include redundant rows and/or columns, and appropriate redundancy control circuitry (32c', 32c').

Method for designing a memory tile for use in a tiled memory

A bit-wise conditional write method and apparatus to minimize power consumption in integrated circuit (IC) magnetoresistive random access memory (MRAM) systems. In a first embodiment, the current logic state of each data bit of a word stored in the MRAM is compared to a corresponding input bit and only those stored data bits which are different are written. In a second embodiment, for each stored data bit which is not being written, the current logic state is guarded against inadvertent modification when other data bits of the word are written. In a third embodiment, if the logic states of a majority of the stored data bits comprising a word are different from the logic states of the respective input bits, the input bits are first complemented so that less than a majority of the stored data bits actually need to be changed, and a complement bit, appended to each word in the MRAM, is set to indicate that the correct logic states of the stored data bits comprising the respective word must be restored upon subsequent readout.

Bit-wise conditional write method and system for an MRAM

Method and apparatus for selecting one of a plurality of banks of registers in a register file of a data processor. The register specifier fields of an instruction are logically combined with respective register bank specifier fields of a control register to access the register file. If register bank specifier fields are provided in the instruction, selection between these bank specifier fields and the bank specifier fields of the control register can be either direct, via a control field in the control register, or indirect, via a control field of the instruction. If the instruction includes an implied register, another register bank specifier field may be provided in the control register for use when the implied register is accessed. The register bank specifier fields, or selected portions thereof, may be made privileged.

Method and apparatus for selecting a register bank

Method and apparatus for selectively inverting memory bits (41-49) in a memory (14). In one embodiment a master reversion bit (75) is used to indicate if all memory bits (41-49) have been inverted. In an alternate embodiment, row reversion bits (77) are used to indicate whether the bits in a corresponding row have been inverted. In yet another embodiment, the reversion column reversion bit (202) may be used to indicate whether the row revert bits (77) themselves have been inverted. These control bits (75, 77, 202) determine whether the output from each column of memory (14) is inverted (i.e. reverted to its original logic state) in order to provide the correct logical state at the data output of memory (14).

Method and apparatus for reducing power dissipation in a

An olfactory card (10) comprises a PC card housing (12) and a PC card connector (14) supported by the PC card housing (12). The olfactory card (10) includes a scent-producing member (20) and an electrical component (24) to activate the scent-producing member (20).

Olfactory card

An apparatus (700) for inhibiting operation of an electronic device (702) during take-off and landing of an aircraft (802) has a sensor (704) that measures a lateral acceleration. A control circuit (706) is coupled to the sensor (704) and has an output (708) coupled to the electronic device (702).

Growing community of inventors

Driftwood, TX, United States of America

Jeffrey Van Myers