Thinking Machines Corporation

Data General Corporation

Siport, Inc.

T. M. Patents, L.p.

Jeffrey V Hill

W Daniel Hillis

Mahesh N Ganmukhi

David C Douglas

Monica C Wong-Chan

Charles E Leiserson

Bradley C Kuszmaul

Robert C Zak, Jr

Shaw-Wen Yang

Guy Lewis Steele, Jr

Sridhar G Sharma

Daniel R Cassiday

Binuraj K Ravindran

Jon P Wade

Robert D Lordi

Zahi S Abuhamdeh

John D Allen

Margaret A St Pierre

Scott J Smith

David S Wells

Monica C Wong

Robert C Zak

Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerate SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.

Processor extensions for accelerating spectral band replication

Enhancements to hardware architectures (e.g., a RISC processor or a DSP processor) to accelerate spectral band replication (SBR) processing are described. In some embodiments, instruction extensions configure a reconfigurable processor to accelerat SBR and other audio processing. In addition to the instruction extensions, execution units (e.g., multiplication and accumulation units (MACs)) may operate in parallel to reduce the number of audio processing cycles. Performance may be further enhanced through the use of source and destination units which are configured to work with the execution units and quickly fetch and store source and destination operands.

A digital computer comprising a plurality of processors interconnected by a network for transferring messages among the processors. At least one processor generates messages of a configuration type. The network comprises a plurality of nodes interconnected in a tree pattern in a series of levels from a lower leaf level to an upper physical root level, with the leaf nodes connected to the processors. Each of the nodes includes a root flag that can be set or cleared in response to a message of the configuration type to establish the node as a logical root. For each node, if the node is a logical root it transfers messages received from a node at a lower level in the tree back down the tree, but if the node is not a logical root it transfers messages received at a lower level node to a higher level node.

Tree network including arrangement for establishing sub-tree having a logical root below the network's physical root

A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.

Massively parallel computer including auxiliary vector processor

A massively-parallel computer includes a plurality of processing nodes and at least one control node interconnected by a network. The network faciliates the transfer of data among the processing nodes and of commands from the control node to the processing nodes. Each each processing node includes an interface for transmitting data over, and receiving data and commands from, the network, at least one memory module for storing data, a node processor and an auxiliary processor. The node processor receives commands received by the interface and processes data in response thereto, in the process generating memory access requests for facilitating the retrieval of data from or storage of data in the memory module. The node processor further controlling the transfer of data over the network by the interface. The auxiliary processor is connected to the memory module and the node processor. In response to memory access requests from the node processor, the auxiliary processor performs a memory access operation to store data received from the node processor in the memory module, or to retrieve data from the memory module for transfer to the node processor. In response to auxiliary processing instructions from the node processor, the auxiliary processor performs data processing operations in connection with data in the memory module.

A digital computer comprises a plurality of processing elements, a communications router, and a control network. Each processing element performs data processing operations in connection with commands, at least some of the processing elements performing the data processing operations in connection with the commands in messages they receive over the control network. Each processing element also generates and receives data transfer messages, each including an address portion containing an address, for transfer to another processing element as identified by the address. At least one of the processing elements further generates the control network messages for transfer over the communications router. The communications router comprises router nodes interconnected in the form of a 'fat-tree,' and the control network comprises control network nodes interconnected in the form of a tree, with the processing elements being connected at the leaf nodes of the respective communications router and control network.

Parallel computer system with physically separate tree networks for data

A computer comprising a plurality of processing nodes, a control node and a request distribution network. Each processing node receives processing requests and generates in response processed data. The control node generates processing requests for transfer to selected ones of the processing nodes as identified by associated request address information, and receives processed data in response, the request address information identifying selected ones of the processing nodes to receive a processing request in parallel. The request distribution network distributes the processing requests to the processing nodes and returns processed data to the control node. The network includes a plurality of request distribution nodes connected in a plurality of levels to form a tree-structure, including an upper root level and a lower leaf level. Each request distribution node is connected to receive processing requests from, and to couple processed data to, a parent, the parent of the request distribution node of the root level comprising the control node, and each request distribution node being further connected to couple processing requests to and receive processed data from, selected children, the children of the request distribution nodes of the leaf level comprising the processing nodes. Each request distribution node, in response to request address information received from its parent, identifies selected ones of its children and thereafter couples further request address information which it receives and processing requests in parallel to its children.

Parallel computer system including request distribution network for

A digital computer includes a plurality of processing elements, a command processor, a diagnostic processor and a communications network. The processing elements each performs data processing and data communications operations in connection with commands. The processing elements also performing diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The command processor generates commands for the processing elements, and also performs diagnostic operations in response to diagnostic operation requests and providing diagnostic results in response thereto. The diagnostic processor generates diagnostic requests. The communication network includes three elements, including a data router, a control network and a diagnostic network. The data router is connected to the processing elements for facilitating the transfer of data among them during a data communications operation. The control network is connected to the processing elements and the command processor for transferring commands from the command processor to the processing elements. The diagnostic network connected to the processing elements, the command processor and the diagnostic processor for transferring diagnostic requests from the diagnostic processor to the processing elements and the command processor and for transferring diagnostic results from the processing elements and the command processor to the diagnostic processor.

Parallel computer system

A communication link interface having an assembly register which is loaded in response to a transmitter's clock rate and unloaded in response to a receiver's clock connected to the interface. The assembly register holds a series of data words received from the communication link. Logic gates or flip flops are provided to insure a time delay between loading the assembly register and unloading it.

Communication link interface with different clock rate tolerance

An initialization or synchronization method in which at least a predetermined number of synchronization messages are sent out over a two-way communication line. The receipt of a synchronization message is awaited before terminating the transmission of synchronization message. After the transmission of synchronization messages has been terminated the receipt of a non-synchronization message will complete the synchronization process. However, certain conditions may cause synchronization to be restarted such as a predetermined number of consecutive error messages, failure to receive any message in a predetermined number of clock signals, receiving more than a predetermined number of synchronization signals, or a reset command.

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San Jose, CA, United States of America

Jeffrey V Hill