Agilent Technologies, Inc.

Other

Jeffrey Thomas Robertson

Gayvin E Stong

Victoria Meier

Paul Douglas Nuber

David James Mielke

William Charles Borough

An apparatus permits built-in self-test ('BIST') of an IC that includes a memory element having more than one impermissible operation. A code generator accepts a clock signal and generates a test code in response to it. A decoder accepts the test code and generates at least two output lines to disable the impermissible operations during the test. When the decoder is in a decode disabled condition, the output lines reflect a value that permit all possible memory operations.

Apparatus and method for random pattern built in self-test

A memory array test system and method provides for testing a memory array in a manufactured chip. In accordance with one aspect of the invention, a system includes memory test input logic that acquires test data via a data port, a memory test enable logic and a memory test output logic. In accordance with another aspect of the invention, a method acquires test data via a data port, writes the test data to a memory address in the memory array, and reads output data from the memory address in the memory array. Then, the method compares the test data and the output data to determine if the memory address in the memory array passes a test.

System and method for testing memory arrays

Generating a data path macro cell based upon a text format template comprising variables. The system provides for creating a text format template by generating a text format representation of a data path macro cell based upon data representing a graphical layout of the data path macro cell. Variables are substituted for constants. Variables are changed to values associated with a macro cell having desired characteristics to create a text format file representative of a desired macro cell. Graphical data representing the layout of a macro cell is generated based upon the text format file.

System for automated generation of data path macro cells

At least one column of a latch array includes a tri-state buffer in the upper portion of the column that receives the output of the uppermost group of latches of the column as its input, and which is enabled by a dump signal when a latch in the upper portion is addressed. When the dump signal that triggers the tri-state buffer is active, whatever is at the input of the tri-state buffer is driven by the buffer to the bottom of the latch array column, thereby providing the driven signal with sufficient strength to obviate transition timing and signal integrity problems. When the dump signal that triggers the tri-state buffer is not asserted, the tri-state buffer output exhibits high impedance, which isolates the lower portion of the latch array column from the upper portion of the latch array column, thereby preventing the capacitance associated with the line connecting the tri-state buffer to the output of the uppermost latch from affecting the driving ability of the latches in the lower portion of the column.

Method and apparatus for ensuring signal integrity in a latch array

A comparnnented storage container for storing and transporting a variety of items, including a closable outer container, a multiplicity of item holders, a plurality of holder carriers, and a carrier receiver assembly. A single item holder or a group of item holders is removably connected to each holder carrier, and a plurality of holder carriers is removably connected to the carrier receiver assembly within the outer container, providing compartmented storage space for a multiplicity of items. Each item holder is constructed in a resealable envelope-like configuration of a transparent material, allowing visual inspection, selection, and removal of an individual item without removing holder carriers or item holders from the outer container. Item holders may be readily removed from and replaced in the outer container in groups or individually.

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Wellington, CO, United States of America

Jeffrey Thomas Robertson