Motorola Corporation

Tokyo Electron Limited

Jeffrey T Wetzel

Dorel Ioan Toma

Eric M Lee

David C Wang

Papu D Maniar

Stanley Michael Filipiak

Sam S Garcia

Arkalgud R Sitaram

Ramnath Venkatraman

John J Stankus

John Mendonca

Mark G Fernandes

Gregory Norman Hamilton

Tze W Poon

An interconnect structure in back end of line (BEOL) applications comprising a tunable etch resistant anti-reflective (TERA) coating is described. The TERA coating can, for example, be incorporated within a single damascene structure, or a dual damascene structure. The TERA coating can serve as part of a lithographic mask for forming the interconnect structure, or it may serve as a hard mask, a chemical mechanical polishing (CMP) stop layer, or a sacrificial layer during CMP.

Structure comprising tunable anti-reflective coating and method of forming thereof

A semiconductor device includes a semiconductor substrate, a film stack formed on the semiconductor substrate and having a film to be processed. A dual hard mask included in the film stack has an amorphous carbon layer and an underlying hard mask layer interposed between the amorphous carbon layer and the film to be processed, the hard mask layer does not include an amorphous carbon layer. A damascene structure for a metal interconnect is formed in the film stack. The amorphous carbon film can, for example, be incorporated within a single damascene structure, or a dual damascene structure. The amorphous carbon film can serve as part of a lithographic mask for forming the interconnect structure, or it may serve as a top layer of a dual hard mask, a chemical mechanical polishing (CMP) stop layer, or a sacrificial layer during CMP.

Structure comprising amorphous carbon film and method of forming thereof

A method for forming a dual inlaid contact structure (damascene) begins by etching dual inlaid contact structures (32, 34, and 36). Masking layers (28) are (228) and the deposition of low-K dielectric material 26 is used to selectively form low-K regions (30) only in critical areas where low-K dielectric material is absolutely needed. Other portions of the wafer remain covered with conventional oxide (24) so that adverse impacts of low-K dielectric material is minimized. Conductive material (38, 40, and 42) is then formed to complete dual inlaid contact structures whereby low-K dielectric plugs (30) reduce cross talk and capacitance within the final structure.

Dual in-laid integrated circuit structure with selectively positioned

A method of forming a semiconductor device by first providing a substrate in a processing chamber. The substrate has an insulating layer and an opening in the insulating layer. A copper barrier layer is formed on the insulating layer and in the opening by providing a plurality of refractory metal atoms and a plurality of silicon atoms in the processing chamber. The atoms are ionized by applying a first bias to the atoms to form a plasma. The substrate is then biased by a first stage bias followed by a second stage bias to accelerate the plasma to the substrate to form the copper barrier layer, where the first stage bias is less than the second stage bias. The copper-containing metal is then deposited on the copper barrier layer over the insulating layer and in the opening. The present invention further includes a semiconductor device formed by the above method.

Semiconductor device with a copper barrier layer and formation thereof

A method for forming semiconductor device (1) that includes providing a substrate (10) having a metal interconnect (12), depositing a via interlevel dielectric (ILD) layer (20) over the substrate (10) and the metal interconnect (12), etching the via ILD layer (20) to form a via (30) over the metal interconnect (12), depositing a trench ILD layer (32) over the via ILD layer (12) and the via (30), etching the trench ILD layer (32) to form a trench (40), the trench (40) being contiguous with the via (12), and depositing a metal (44) so as to fill the via (30) and the trench (40), and provide electrical connection with the metal interconnect (12).

Method of forming a semiconductor device having dual inlaid structure

A transition-metal silicide process includes the formation of a boron nitride capping layer overlying a transition-metal layer. In one embodiment, a transition-metal layer (30) is deposited onto a silicon surface (22), and onto a polysilicon gate electrode (12). A capping layer (32), which can be either boron nitride or boron oxynitride is deposited onto the transition-metal layer (30), and an annealing process is carried out to form a transition-metal/silicon alloy layer (34, 36, 38) at the silicon surface (22), and on the gate electrode (12). The capping layer (32) overlies the transition-metal layer (30) during the annealing process and prevents the formation of an oxide layer at the silicon surfaces (22, 12). After the annealing process is complete, the capping layer (13) is removed by a selective wet etch process, and a second annealing step is carried out to form a transition-metal silicide layer (40, 42, 44).

Process for fabricating a silicide layer in a semiconductor device

A method for forming a patterned layer of material begins by providing a substrate (12). A device layer (14) is formed overlying the substrate (12). A layer (16) is formed over the device layer (14). Layer (16) is further characterized as being an inorganic dielectric material, such as a plasma enhanced silicon nitride (PEN) material. A mask (18) is positioned adjacent the layer (16). Ultra-violet (UV) light (20) is selectively exposed to the layer (16) through the mask (18). Exposure from the UV light (20) forms exposed regions (16b) and unexposed regions (16a) of the layer (16). The UV light (20) alters an atomic bonding energy of hydrogen atoms within the exposed regions (16b) while not altering unexposed regions (16a). The layer (16) is exposed to an etchant which etches the exposed regions (16b) and unexposed regions (16a) at different rates. The etching forms a patterned layer from the layer ( 16) which may be used as a masking layer.

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Austin, TX, United States of America

Jeffrey T Wetzel