Motorola Corporation

Jeffrey T Bridges

Paul C Rossbach

Jeffrey E Maguire

Lawrence W Osborne

A pointer (86) has generate circuitry (90), propagate circuitry (90), carry circuitry (90) and detector circuitry (92). The pointer is for use with a buffer to designate one of a plurality of entries of the buffer. The generate circuitry receives a first and a second data word and generates a plurality of local generate functions. One bit of the first data word, second data word, and one of the local generate functions each corresponds to one of the entries of the buffer. Each data bit of the first data word is representative of the eligibility of the pointer to designate an entry. The second data word is representative of the pointer location at a previous time. The propagate circuitry receives the first and second data words and generates a plurality of local propagate functions. Each local propagate function corresponds to one of the entries of the buffer. The carry circuitry is coupled to the generate circuitry and to the propagate circuitry and generates a plurality of carry bits. Each carry bit corresponds to one of the entries of the buffer. The detector circuitry is coupled to the carry circuitry and detects a predetermined pattern within the plurality of carry bits. The output of the detector circuitry is coupled to the second data word. The pointer may be designed in modules. A modular design procedure makes the pointer easily adapted for applications with different size buffers while maintaining the pointer's high speed performance.

Pointer for use with a buffer and method of operation

A precharge device (28) has a first (30) and a second node (32), a transistor tree (29), a screening transistor (Q20) and clocking circuitry (Q17, Q18, Q19). The transistor tree (29) couples the first (30) and the second (32) node and is operable to electrically short-circuit the nodes according to input signals (A.sub.1, A.sub.2, A.sub.3). The screening transistor (Q20) has a first and a second [source-drain region] current electrode and a [gate] control electrode. The first [source-drain region] current electrode is coupled to a third node (34), the second [source-drain region] current electrode is coupled to the second node (32) and the [gate] control electrode is coupled to the first node (30). The clocking circuitry alternately precharges the first (30) and third nodes (34) to a first known voltage level and evaluates the voltage on the first node (30) to output a logic level.

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Austin, TX, United States of America

Jeffrey T Bridges