Skhynix Inc.

Jeffrey Song

Seong Won Shin

Yi Tong

Sean Lee

A controller of a memory system controls a completion rate of commands. The controller receives, from a host, command requests to be processed on a memory device. The controller processes the command requests, determines a first number of completion notifications, which are to be transmitted to the host in a first time interval, among multiple completion notifications associated with the command requests, based on a throughput credit, a set maximum credit, and the number of the multiple completion notifications. The controller transmits, to the host, the first number of completion notifications in the first time interval, and transmits a second number of completion notifications in the second time interval.

Systems and methods for controlling completion rate of commands

Within a memory system, architecture and operations for processing commands in a parity cache scheme support more open blocks taking into account cost and performance. Dynamic random access memory space holds parity buffers of all open blocks and communicates with a cache and cache controller. An open block queue (OBQ) accumulates commands in separate queues for each open block to increase cache hit rate. Open block counters keep track of the number of commands for each OBQ to facilitate arbitration. A unique identification (ID) is given for each open block.

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Jeffrey Song