Qualcomm Incorporated

Jeffrey Shabel

Bohuslav Rychlik

Wesley James Holland

George Patsilaras

Simon Peter William Booth

Andrew Edmund Turner

Rashmi Kulkarni

Robert Hardacker

Nhon Toai Quach

Rahul Gulati

Mainak Biswas

Christopher Cooper Riddle

Subbarao Palacharla

Girish Bhat

Philip T Mueller, Jr

Huang Huang

Kedar Bhole

Songhe Cai

Pranjal Bhuyan

Ling Feng Huang

Vipul Gandhi

Satish Anand

Isaac Berk

Chih-Chi Cheng

Zhurang Zhao

Sparsh Singhai

Mattheus Heddes

Carl Victor Streeter

Integrated circuits (ICs) employ subsystem shared cache memory for facilitating extension of low-power island (LPI) memory. An LPI subsystem and primary subsystems access a memory subsystem on a first access interface in a first power mode and the LPI subsystem accesses the memory subsystem by a second access interface in the low power mode. In the first power mode, the primary subsystems and the LPI subsystem may send a subsystem memory access request including a virtual memory address to a subsystem memory interface of the memory subsystem to access either data stored in an external memory or a version of the data stored in a shared memory circuit. In the low-power mode, the LPI subsystem sends an LPI memory access request including a direct memory address to an LPI memory interface of the memory subsystem to access the shared memory circuit to extend the LPI memory.

Integrated circuits (IC) employing subsystem shared cache memory for facilitating extension of low-power island (LPI) memory and related methods

In some aspects, the present disclosure provides a method for managing a command queue in a universal flash storage (UFS) host device. The method includes determining to power on a first subsystem of a system-on-a-chip (SoC), wherein the determination to power on the first subsystem is made by a second subsystem of the SoC based on detection of user identity data contained in a first image frame during an initial biometric detection process. In certain aspects, the second subsystem is configured to operate independent of the first subsystem and control power to the first subsystem. In certain aspects, the second subsystem includes a second optical sensor, a set of ambient sensors, and a second processor configured to detect, via a set of ambient sensors, an event comprising one or more of an environmental event outside of the device or a motion event of the device.

Multi-stage biometric authentication

In one aspect, space in a tile-unaware cache associated with an address aperture may be managed in different ways depending on whether a processing component initiating an access request through the aperture to a tile-based memory is tile-unaware or tile-aware. Upon a full-tile read by a tile-aware process, data may be evicted from the cache, or space may not be allocated. Upon a full-tile write by a tile-aware process, data may be evicted from the cache. In another aspect, a tile-unaware process may be supplemented with tile-aware features by generating a full tile of addresses in response to a partial-tile access. Upon a partial-tile read by the tile-unaware process, the generated addresses may be used to pre-fetch data. Upon a partial-tile write, the addresses may be used to evict data. Upon a bit block transfer, the addresses may be used in dividing the bit block transfer into units of tiles.

System and method for mixed tile-aware and tile-unaware traffic through a tile-based address aperture

An intelligent tile-based prefetching solution executed by a compression address aperture services linearly addressed data requests from a processor to memory stored in a memory component having a tile-based address structure. The aperture monitors tile reads and seeks to match the tile read pattern to a predefined pattern. If a match is determined, the aperture executes a prefetching algorithm uniquely and optimally associated with the predefined tile read pattern. In this way, tile overfetch is mitigated while the latency on first line data reads is reduced.

System and method for intelligent tile-based prefetching of image frames in a system on a chip

Systems and methods are disclosed for error correction control (ECC) for a memory device comprising a data portion and an ECC portion, the memory device coupled to a system on a chip (SoC). The SoC includes an ECC cache. On receipt of a request to write a line of data to the memory, a determination is made if the data is compressible. If so, the data line is compressed. ECC bits are generated for the compressed or uncompressed data line. A determination is made if an ECC cache line is associated with the received data line. If the data line is compressible, the ECC bits are appended to the compressed data line and the appended data line is stored in the data portion of the memory. Otherwise, the ECC bits are stored in the ECC cache and the data line is stored in the data portion of the memory.

Systems and methods for implementing error correcting code in a memory

Systems and methods for external access detection and recovery in a subsystem of a system-on-a-chip (SoC) in a portable computing device (PCD) are presented. In operation, a subsystem of the SoC is operated in an internal mode independently of the SoC while the SoC is in a low power state, such as a non-functional or zero power state or mode. The subsystem comprises a processor in communication with a memory, a sensor, and a monitor module. The monitor module detects when the processor of the subsystem requests access to a component external to the subsystem. In response to this detected request, the SoC is caused to enter into a full power state or mode, and the subsystem is caused to exit the internal mode of operation.

System and method for system-on-a-chip subsystem external access detection and recovery

A method of a method of adjusting an intensity of a backlight of a display is disclosed. The method includes dimming a backlight that illuminates a display of an electronic device in response to a task initiated by a user. The method also includes, prior to the task completing, automatically adjusting an intensity of the backlight based on a progress of the task.

Adjusting backlight intensity based on a progress of a task

Growing community of inventors

San Diego, CA, United States of America

Jeffrey Shabel