International Business Machines Corporation

Jeffrey Scott Zimmerman

Terence B Hook

Wolfgang Sauter

Jeffrey P Gambino

Timothy Harrison Daubenspeck

Christopher David Muzzy

Baozhen Li

Timothy Dooling Sullivan

Thomas L McDevitt

Jonathan Daniel Chapple-Sokol

Christopher A Ponsolle

Bette B Reuter

John Atkinson Fifield

John J Ellis-Monaghan

Kirk David Peterson

Kerry Bernstein

Norman Jay Rohrer

Thomas Anthony Wassick

Christopher P Miller

Robert E Busch

Andrew A Turner

George W Rohrbaugh, Iii

Henry A Bonges, Iii

Mark R Bilak

William F Pokorny

Gerald P Pomichter

Robert C Redburn

John Jay Maloney

Timothy J O'Gorman

Joseph M Forbes

Curt Guenther

Michael J Maloney

Michael D Maurice

Regis D Parent

Disclosed herein is a method for failure signature detection in a semiconductor comprising generating defect signatures for failing latches from a plurality of integrated circuit chips; generating a latch to mask relationship for the failing latches; generating maximally descriptive masks into identities; generating a list of identities for comparison; determining commonalities between the lists of identities; and generating details about differences and commonalities within the defect signatures.

Method for enhanced semiconductor product diagnostic fail signature detection

A design structure is embodied in a machine readable medium for designing, manufacturing, or testing a design. The design structure includes a dielectric material formed between a design sensitive structure and a passivation layer. The design sensitive structure comprising a lower wiring layer electrically and mechanically connected to a higher wiring level by a via farm. A method and structure is also provided.

Structure, semiconductor structure and method of manufacturing a semiconductor structure and packaging thereof

Aspects of the invention provide for masking a current profile of a one-time programmable (OTP) memory. In one embodiment, a circuit includes: a first one-time programmable (OTP) memory configured to receive a data input for a plurality of address fields; and a second OTP memory configured to receive an inverse of the data input for a plurality of address fields, wherein a current profile for a programming supply for the first OTP memory and the second OTP memory is masked, such that the data input for the first OTP memory is undetectable.

Protection of one-time programmable (OTP) memory

A failure analysis tool, a method of using the tool and a design structure for designing a mask for protecting a critical area of wiring failure in a semiconductor chip during packaging is provided. The failure analysis tool includes a computer infrastructure operable to determine a risk area for wiring layer failure during solder bump formation by determining a distance from a center of a chip to a location for a solder bump processing and identifying an area at an edge of the location for the solder bump processes at a predetermined distance and greater from the center of the chip.

Structure, failure analysis tool and method of determining white bump location using failure analysis tool

The invention generally relates to a design structure of a circuit design, and more particularly to a design structure of a delamination sensor for use with low-k materials. A delamination sensor includes at least one first sensor formed in a layered semiconductor structure and a second sensor formed in the layered semiconductor structure. The at least one first sensor is structured and arranged to detect a defect, and the second sensor is structured and arranged to identify an interface where the defect exists.

Sensor, method, and design structure for a low-k delamination sensor

A method is disclosed of determining allowable antenna limits for semiconductor-on-insulator (SOI) technology. In one embodiment, the method may include: determining antenna area on a gate; determining antenna area on a source/drain; determining a total gate insulator area between gate and source/drain nets; and calculating allowable antenna area as a function of the total gate insulator area between the nets such that a larger total antenna area is allowed for larger total gate insulator area between the nets.

Determining allowance antenna area as function of total gate insulator area for SOI technology

A structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

Suppression of localized metal precipitate formation and corresponding metallization depletion in semiconductor processing

A method and structure for suppressing localized metal precipitate formation (LMPF) in semiconductor processing. For each metal wire that is exposed to the manufacturing environment and is electrically coupled to an N region, at least one P+ region is formed electrically coupled to the same metal wire. As a result, few excess electrons are available to combine with metal ions to form localized metal precipitate at the metal wire. A monitoring ramp terminal can be formed around and electrically disconnected from the metal wire. By applying a voltage difference to the metal wire and the monitoring ramp terminal and measuring the resulting current flowing through the metal wire and the monitoring ramp terminal, it can be determined whether localized metal precipitate is formed at the metal wire.

A method for preventing charging damage during manufacturing of an integrated circuit design, having silicon over insulator (SOI) transistors. The method prevents damage from charging during processing to the gate of IC devices by assigning regions to the IC design such that the devices located within the regions have electrically independent nets, identifying devices that may have a voltage differential between the source or drain, and gate as susceptible devices within a given region, and connecting a element across the respective source or drain, and the gate of each of the susceptible devices such that the element is positioned within the region. The method includes connecting compensating conductors to an element to eliminate potential charging damage.

Method of assessing potential for charging damage in integrated circuit designs and structures for preventing charging damage

A method and apparatus for determining the complete coverage of a passivating material on the final conductive interconnection of a wafer containing integrated circuits. A test structure with the dimensions of the final interconnections of the integrated circuits is formed during manufacture of the integrated circuits and used to determine complete coverage of the wafer by creating an opening in the passivating material at the test structure, the size of the opening being indicative of the complete coverage of the wafer.

Method and apparatus for completely covering a wafer with a passivating material

A halo implant method for forming halo regions of at least first and second transistors formed on a same semiconductor substrate. The first transistor comprises a first gate region disposed between first and second semiconductor regions. The second transistor comprises a second gate region disposed between third and fourth semiconductor regions. The method comprises the steps of, in turn, halo-implanting each of the first, second, third, and fourth semiconductor regions, with the other three semiconductor regions being masked, in a projected direction which (i) is essentially perpendicular to the direction of the respective gate region and (ii) points from the halo-implanted semiconductor region to the respective gate region.

Halo implant in semiconductor structures

A method for creating a guardband that incorporates statistical models for test environment, system environment, tester-to-system offset and reliability into a model and then processes a final guardband by factoring manufacturing process variation and quality against yield loss.

Statistical guardband methodology

A domino circuit design for handling high stress conditions. The domino logic circuit includes a programmable mechanism for choosing whether the circuit is operating during normal operations or during a stress test, such as a burn-in procedure. In particular, the circuit includes a dual purpose transistor that is controllable by either a precharge signal or an output signal, and includes a mechanism for selecting whether the precharge signal or the output signal is to control the gate input of the dual purpose transistor. Accordingly, the dual purpose transistor will either act in parallel with the precharge device, or a keeper device depending on the mode of operation chosen.

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Swanton, VT, United States of America

Jeffrey Scott Zimmerman