Broadcom Corporation

Jeffrey Scott Putnam

Loke Kun Tan

Henry Samueli

Jonathan S Min

Tak Kwan Lee

Thuji Simon Lin

Tracy C Denk

James P Cavallo

Ramon Alejandro Gomez

Avi Kliger

Leo Montreuil

Robindra B Joshi

Ravikiran Rajagopal

Hong Liu

Ravi Rajagopal

Paul T Yang

Thomas J Kolze

Bruce Joseph Currivan

Fang Lu

Kevin Lee Miller

Ravi Bhaskaran

Gopal Triplicane Venkatesan

Hsin-An Liu

An auxiliary reduced power analog-to-digital converter (ADC) is provided for use during sleep periods of a receiver. The auxiliary ADC has a reduced dynamic range but sufficient accuracy to allow demodulation of signaling information contained in an input signal and to update control parameters used for synchronization and channel estimation. As such, a main higher power, higher dynamic range ADC can be turned off during sleep periods, reducing receiver power consumption. The main ADC is turned on at the end of a sleep period, and the receiver can be ready for receiving data immediately using the main ADC because the control parameters are maintained up to date during the sleep period using the auxiliary ADC.

Receiver with reduced wake-up time

A communication device is operative to generate and orthogonal frequency division multiplexing (OFDM) symbol that includes one or more data and ranging modulation symbols. The data and ranging modulation symbols may be included within different sub-carriers of the OFDM symbol. The OFDM symbol is used to generate an OFDM symbol pair in the frequency domain (FDOM). After conversion from the FDOM to the time domain (TDOM), the OFDM symbol pair may then undergoes post-processing in the TDOM before transmission. Such post-processing may include the addition of cyclic prefix (CP) and cyclic suffix (CS) to the OFDM symbol pair in the TDOM as well as filtering using a window function. The OFDM symbol may be generated as an orthogonal frequency division multiple access (OFDMA) symbol, and two were more OFDM symbols or OFDMA symbols may be arranged in a frame.

OFDM or OFDMA signaling for ranging and data

A method of compensating for carrier frequency and phase errors of a received multi-carrier modulated signal. The received multi-carrier signal including modulated carriers for transmitting known data and unmodulated carriers for error correction, comprising, time domain down converting the received multi-carrier signal to base-band to provide a down-converted signal, the down-converted signal including a plurality of modulated carriers for transmitting known data and unmodulated carriers for error correction. Sampling an unmodulated carrier of the down-converted signal to provide received data samples. Providing a reference signal derived from the unmodulated carrier of the down-converted signal. And, estimating phase errors from a phase difference between the ummodulated carrier and the reference signal derived from the unmodulated carrier of the down-converted signal to provide a plurality of received sample phase error estimates for each modulated carrier.

System and method for multi-carrier modulation

A clock signal regeneration system and method to adjust the phase of a frequency-locked clock signal is provided. The system includes a numerically controlled oscillator, a clock source, and an adder. In one embodiment, additional components are included in the system to ensure that underflow or overflow of the numerically controlled oscillator is prevented. In another embodiment, additional components are included to ensure that output pulses from the numerically controlled oscillator do not occur within a minimum time interval. The method includes deriving a phase adjustment factor, adding the phase adjustment factor to a frequency control word, providing the modified frequency control word to a numerically controlled oscillator and generating a phase shifted, frequency-locked output signal.

System and method for adjusting the phase of a frequency-locked clock

Methods and apparatus for reducing precision of an input signal, by comparing a portion of the input signal to a preselected threshold value, and determining a selectable bias responsive to the comparison. By combining a portion of the input signal with the selectable bias, a reduced precision signal, having minimized or eliminated rounding error, is generated. The selectable bias corresponds to a predetermined characteristic of one of bias, an error signal, the input datum, the reduced precision datum, and a combination thereof.

Apparatus and method for reducing precision of data

Carrier signals modulated by information (video and/or data) signals are received through a cable and are converted to modulated signals at an intermediate frequency. The IF signals are sampled at a particular frequency to produce digital information signals. The digital information signals are introduced to a variable interpolator which produces first digital signals. The first digital signals are introduced to a complex multiplier which produces second digital signals. The second digital signals pass to an adaptive equalizer which selects for each of the second signals in accordance with the amplitude of such second signals, an individual one of a multitude of amplitude levels involved in quadrature amplitude modulation. These selected amplitude levels represent the information (video and/or data). The output signals from the adaptive equalizer are introduced to a first signal recovery loop which includes a first numerically controlled oscillator. The oscillator operates upon the variable interpolator to obtain the production by the variable interpolator of the first digital signals in the correct subinterval of the time period that each of the digital information signals is produced. The output signals from the adaptive equalizer are also introduced to a second signal recovery loop which includes a second numerically controlled oscillator. This oscillator operates upon the complex multiplier to maintain the frequency of the second digital signals at the frequency of the digital information signals.

Multi-mode variable rate digital cable receiver

All digital reference frequency locking. An all digital approach is provided for operation within one or more CMs within a cable modem communication system to lock the upstream of the one or more CMs to the downstream symbol clock provided from a CMTS. The locking of the CM's upstream may be performed using one of at least three different functions: (1) Locking the upstream symbol clock phase to the downstream symbol clock phase, (2) Locking the downstream symbol clock phase to the headend reference clock phase (typically 10.24 MHz or integer multiple thereof), and (3) Locking the upstream carrier frequency to the downstream symbol clock frequency. The all-digital techniques for supporting all digital reference frequency locking functionality provide high performance to support S-CDMA and other synchronous modulation techniques.

All digital reference frequency locking

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Irvine, CA, United States of America

Jeffrey Scott Putnam