Silicon Graphics, Incorporated

Atheros Communications, Inc.

Silicon Graphics International Corporation

Hewlett Packard Enterprise Development LP

Qualcomm Atheros Inc.

Atheros, Inc.

Jeffrey Scott Kuskin

William A Huffman

Tao-Fei Samuel Ng

Andrew Mackinnon Davidson

Steven C Miller

Daniel E Lenoski

Michael S Woodacre

Deepak Dhamdhere

Fiona Cain

Jeffrey M Gilbert

Michael Brian Galles

Gregory Michael Thorson

Deepak Prabhakar Dhamdhere

Fiona J Cain

Tao-Fei S Ng

A processor () in a distributed shared memory multi-processor computer system () may initiate a flush request to remove data from its cache. A processor interface () receives the flush request and performs a snoop operation to determine whether the data is maintained in a one of the local processors () and whether the data has been modified. If the data is maintained locally and it has been modified, the processor interface () initiates removal of the data from the cache of the identified processor (). The identified processor () initiates a writeback to a memory directory interface unit () associated with a home memoryfor the data in order to preserve the modification to the data. If the data is not maintained locally or has not been modified, the processor interface () forwards the flush request to the memory directory interface unit (). Memory directory interface unit () determines which remote processors within the system () have a copy of the data and forwards the flush request only to those identified processors. The identified processors then remove the data from their respective caches in response to the flush request. If an identified remote processor has modified data, the identified remote processor initiates a writeback to the memory directory interface unit () for preservation of the modified data.

System and method for removing data from processor caches in a distributed multi-processor computer system

A processor interface () receives a flush request from a processor () and performs a snoop operation to determine whether the data is maintained in a one of the local processors () and whether the data has been modified. If the data is maintained locally and it has been modified, an identified local processor () receives the flush request from the processor interface () and initiates a writeback to a memory directory interface unit (). If the data is not maintained locally or has not been modified, the processor interface () forwards the flush request to the memory directory interface unit (). Memory directory interface unit () determines which remote processors within the system () have a copy of the data and forwards the flush request only to those identified processors.

To efficiently transmit data on a wireless network, small packets that might otherwise be sent individually are aggregated into a 'superframe'. This superframe can then be transmitted as a single, larger packet. To form this superframe, a plurality of tagged data packets can be aggregated into a packed aggregation block (PAB). Encapsulation data, e.g. protocol information, can be appended to the PAB. Wireless transmission information can bound the PAB and encapsulation data. Forming the superframe can be performed using an efficient combination of hardware and software. In one embodiment, aggregation of the tagged data packets can be performed by hardware without regard to the underlying protocol(s). Software can then provide protocol-handling support.

Efficient data transmission by data aggregation

A transmitting apparatus and method is described that determines, on a frame-by-frame basis, whether to transmit a compressed frame or a non-compressed frame, depending upon whether the compressed frame or the non-compressed frame will actually be smaller in size. The frame that is smaller is indicated for transmission, with a header of the frame being adapted to include a compression flag indicating whether that frame is the compressed or the non-compressed frame. After wireless transmission and reception, the received frame is, if needed, decompressed if so indicated by the compression flag.

Method and apparatus for transmitting and receiving compressed frame of data over a wireless channel

A method and system for managing memory in a multiprocessor system includes defining the plurality of processor coherence domains within a system coherence domain of the multiprocessor system. The processor coherence domains each include a plurality of processors and a processor memory. Shared access to data in the processor memory of each processor coherence domain is provided only to elements of the multiprocessor system within the processor coherence domain. Non-shared access to data in the processor memory of each processor coherence domain is provided to elements of the multiprocessor system within and outside of the processor coherence domain.

Method and system for managing memory in a multiprocessor system

A key-caching system retrieves actively used keys from a relatively fast cache memory for fast processing of wireless communications. Additional keys are stored in relatively slow system memory that has high storage capacity. As keys become needed for active use, the keys are retrieved from the system memory and stored in the cache memory. By using active memory for keys actively being used, system performance is enhanced. By using system memory for keys not being used, a greater number of keys are available for transfer to the cache and subsequent active use.

Key caching system

To efficiently personalize multiple bus interfaces, an input/output (I/O) integrated circuit (IC) is provided. This I/O IC can include two local bus control blocks, wherein each local bus control block can be configured to provide a selected personality. The selected personality can include an IDE (intelligent drive electronics) interface, an MPEG-TS (Moving Picture Experts Group Transport Stream) interface, a GPIO (general purpose input/output) interface, or a PCI (peripheral component interconnect) interface. Advantageously, when the two local bus control blocks are configured, they can provide one of a combined IDE/MPEG-TS interface, a combined IDE/GPIO interface, and the PCI interface. Thus, the I/O IC has a common set of pins that can be allocated to one or more bus types, depending on net pin count.

Multiple personality I/O bus

Providing shared and non-shared access to memory in a system with plural processor coherence domains

A Hardware MAC (Media Access Control) unit implements time-critical functions according the 802.11 standard for telecommunications, thereby enhancing system performance. The MAC layer includes three sub-layers: MLME (MAC Sublayer Management Entity), which connects the MAC unit with the host CPU, FTM (Frame Transition Manager), which connects the MAC unit with the network, and FLPM (Frame Level Protocol Manager), which internally connects the MLME sub-layer with the FTM sub-layer. In particular, the FLPM manager includes time-critical and non-time-critical functions that are customarily implemented in software on the MAC by a MAC CPU (Central Processing Unit). The hardware MAC implements time-critical FLPM functions in hardware on the MAC and implements non-time-critical FLPM functions in software on the host CPU so that requirements for processing software on the MAC preferably may be altogether eliminated or alternatively may be substantially reduced.

Hardware MAC

A method of queue management includes: adding entries having a first priority to a first software queue; adding entries having a second priority to a second software queue; reading entries from the first software queue to a physical queue; at a threshold time, flushing entries from the physical queue; after the act of flushing the physical queue, reading entries from the second software queue to the physical queue until a termination criterion is satisfied; after the termination criterion is satisfied, reading entries from the first software queue to the physical queue; and transmitting entries from the physical queue to a network.

System and method for interleaving frames with different priorities

A processor () issues a read request for data. A processor interface () initiates a local search for the requested data and also forwards the read request to a memory directory () for processing. While the read request is processing, the processor interface () can determine if the data is available locally. If so, the data is transferred to the processor () for its use. The memory directory () processes the read request and generates a read response therefrom. The processor interface () receives the read response and determines whether the data was available locally. If so, the read response is discarded. If the data was not available locally, the processor interface () provides the read response to the processor ().

System and method for reducing memory latency during read requests

A processor () in a distributed shared memory computer system () receives ownership of data and initiates an initial update to memory request. A front side bus processor interface () forwards the initial update to memory request to a memory directory interface unit (). The front side processor interface () may receive subsequent update to memory requests for the data from processors co-located on the same local bus. Front side bus processor interface () maintains a most recent subsequent update to memory in a queue (). Once the data has been updated in its home memory (), the memory directory interface unit () sends a writeback acknowledge to the front side bus processor interface (). The most recent subsequent update to memory request in the queue () is then forwarded by the front side bus processor interface () to the memory directory interface unit () for processing.

System and method for handling updates to memory in a distributed shared memory system

A partitioned computer system () includes a plurality of node controllers () connected by a network () and partitioned into a plurality of partitioned groups (). A requesting node controller () in one partitioned group () requests a latest copy of a line in a memory () in a separate partitioned group (). A storing node controller () in the separate partitioned group () holding the latest copy of the line in its memory () is identified. The requesting node controller () transmits its request for a coherent copy of a line to the storing node controller (). The storing node controller () transmits the latest copy of the line in response to the request to the requesting node controller () without including the requester in a sharer-tracking process.

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Mountain View, CA, United States of America

Jeffrey Scott Kuskin