Cypress Semiconductor Corporation

Jeffrey Scott Hunt

Satish C Saripella

Donald Y Yu

William Randolph Hiltpold

An input buffer circuit has a pass gate circuit coupled to an input. A pseudo-differential amplifier is coupled to the pass gate circuit. A level shifter is coupled to the pseudo-differential amplifier.

Input buffer circuit

An improved high-speed sense amplifier is disclosed for use in programmable logic devices (PLDs) and complex PLDs. The sense amplifier includes a transresistance amplifier portion that provides a voltage potential to a first node of a memory array, which defines a read product term line. The current drawn by the memory array will cause the output of the amplifier to change states once a predetermined current level is reached, the predetermined trip point indicating that at least one memory cell is conducting. The amplifier includes an n-channel MOS transistor having its drain connected between a second node of the memory array, and its source to ground. The gate of the n-channel transistor is connected to the read product line. The n-channel limits current through the memory array by raising the potential at the second node, thus reducing the voltage drop across the memory array. The sense amplifier also includes a depletion MOS transistor having its drain connected to the read product term line, its source to ground, and its gate to the drain of the n-channel transistor. As branches of the memory cell become conductive, the voltage of the drain of the n-channel transistor rises, which biases the depletion transistor on, drawing current from the sense amplifier. This extra current eliminates the 'strong zero' to 'weak zero' glitch that can occur when many conducting legs change to a single conducting leg.

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Ackerman, MS, United States of America

Jeffrey Scott Hunt