Intel Corporation

Jeffrey S Wilder

Krishnakanth Venkata Sistla

Ravishankar Iyer

Ankush Varma

Vivek Garg

Ian M Steiner

Donald K Newell

Zhen Fang

Martin Rowland

Matthew M Bace

Sadagopan Srinivasan

Liqun Cheng

An apparatus and method for managing a frequency of a computer processor. The apparatus includes a power control unit (PCU) to manage power in a computer processor. The PCU includes a data collection module to obtain transaction rate data from a plurality of communication ports in the computer processor and a frequency control logic module coupled to the data collection module, the frequency control logic to calculate a minimum processor interconnect frequency for the plurality of communication ports to handle traffic without significant added latency and to override the processor interconnect frequency to meet the calculated minimum processor interconnect frequency.

Method and apparatus for setting an I/O bandwidth-based processor frequency floor

In an embodiment of the present invention a method includes: sending request for data to a memory controller; arranging the request for data by order of importance or priority; identifying a source of the request for data; and if the source is an input/output device, masking off P ways in a cache; and allocating ways in filling the cache. Other embodiments are described and claimed.

Searching a shared cache by using search hints and masked ways

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Olympia, WA, United States of America

Jeffrey S Wilder