Micron Technology Incorporated

Jeffrey S Mailloux

Todd A Merritt

Kevin J Ryan

Brett L Williams

Eugene H Cloud

Glen Earl Hush

Ward D Parkinson

An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs. Additionally, a DRAM is provided having both pipelined and burst Extended Data Out modes of operation and the ability to switch between them.

Asynchronously-accessible memory device with mode selection circuitry for burst or pipelined operation

Memory device for burst or pipelined operation with mode selection circuitry

An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs. Additionally, a DRAM is provided having both pipelined and burst Extended Data Out modes of operation and the ability to switch between them. Additionally, a memory device switchable between a patterned and a patternless addressing scheme is provided.

Burst/pipelined edo memory device

Method for switching between modes of operation

A Mask Write mode for a semiconductor memory responds to an enable command. This permits a by-four chip to provide parity information for four sectors of memory. The invention allows the latching of mask data on a rising edge of CAS so that new mask data can be entered in Page Mode.

Mask write enablement for memory devices which permits selective masked

A three port memory device has two serial ports and a random access memory port. The random access memory port is addressed to a random access memory in a conventional manner, using RAS and CAS address signals. Data may also be supplied and retrieved through two serial ports to a pair of serial access memories for transfer between the serial ports and the random access memory. This configuration permits formatted data to be simultaneously assessed through the two serial ports, while the random access memory port is being accessed.

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Boise, ID, United States of America

Jeffrey S Mailloux