Lsi Logic Corporation

Other

Honeywell G.m.b.h.

Lsi Corporation

Jeffrey S Kueng

Brett D Hardy

Cynthia M Kueng

Lane Allen Smith

Vladimir Sindalovsky

Michael O Jenkins

Roger L Roisen

Prashant K Singh

Donald C Grillo

Justin J Kraus

In described embodiments, a receiver includes a clock and data recovery (CDR) circuit with a voltage control oscillator (VCO) having proportional and integral loop control, and a Lock to Reference (L2R) mode circuit using Phase and Frequency Detector (PFD) control of the VCO during the absence of input data to the CDR. A regular CDR second order loop incorporating PFD control of the VCO during the absence of input data to the CDR achieves relatively rapid lock to reference when compared to counter-based lock to reference mode of operation.

CDR with digitally controlled lock to reference

An over-voltage protected integrated circuit is provided, which includes a discharge node, an input-output pad, a signal trace, which is coupled to the input-output pad, and a pair of back-to-back diodes, which is coupled between the first signal trace and the discharge node.

ESD protection circuit for low amplitude signals

An integrated circuit input buffer is provided, which includes a differential buffer, first and second average value circuits and a feedback amplifier. The input buffer is selectively operable in a differential operating mode and a single-ended operating mode. The differential amplifier has first and second buffer inputs and first and second buffer outputs. The first and second average value circuits have inputs coupled to the first and second buffer outputs, respectively. The feedback amplifier has first and second differential inputs coupled to outputs of the first and second average value circuits, respectively, and has an amplifier output. The amplifier output is coupled to the second buffer input when the input buffer is in the single-ended operating mode and is decoupled from the second buffer input when the input buffer is in the differential operating mode.

Combined differential and single-ended input buffer

Method for forming a CMOS transistor in a silicon layer positioned above an underlying buried oxide layer including isolating a first active area and a second active area; forming an n-well and a p-well having specified back gate threshold voltages; forming gates over the wells; forming a lightly doped drain region in the p-well that extends through the silicon layer; and implanting ions to form a source and a drain region in the p-well to provide a lightly doped drain drift region.

Method of making SOI circuit for higher temperature and higher voltage

A putting accuracy training aid providing an elongated, flat rolling surface and a non-slip base. A recessed tee supports a ball forward of an adjustable stroke gauge and elastomer limit stop. Inclined surfaces, projections and/or grooves provided adjacent the tee facilitate re-teeing without stooping. Jointed multi-section constructions are also disclosed having a sectional body and/or wing attachments.

Golf putting trainer

Putting aid

Growing community of inventors

New Brighton, MN, United States of America

Jeffrey S Kueng