Oracle International Corporation

Oracle America, Inc.

Sun Microsystems, Inc.

Intrinsity, Inc.

International Business Machines Corporation

Other

Napa Technology

Jeffrey S Brooks

Christopher Hans Olson

Robert T Golla

James S Blomgren

Paul Joseph Jordan

Paul J Jagodik

Terence M Potter

Yuan C Chou

Josephus Ebergen

Hesam Fathi Moghadam

Morris Taradalsky

Jared C Smolens

Nick Moezidis

Austin Lee

Ross Rittiman

Eugene Karichkin

Manish K Shah

Shasank Kisan Chavan

Rabin Sugumar

Hoichi Cheong

Martin Stanley Schmookler

Jama Ismail Barreh

Matthew B Smittle

Howard L Levy

Sadar U Ahmed

David L Weaver

Edward A Vetter

Tiberiu Carol Galambos

Terry Dean Blackwell

Stephen L Dohanich

Albert Danysh

Prateek Agrawal

Andrew Ewoldt

David E Kreml

Josephus C Ebergen

Embodiments of a processing pipeline for converting numbers formatted in a machine independent format to a machine compatible format are disclosed. In response to execution of a conversion instruction, the processing pipeline may convert each digit of a number in a machine independent format number to generate converted digits. Using the converted digits, the processing pipeline may generate multiple intermediate products. The processing pipeline may then combine the intermediate products to generate a result number that is formatted with a machine compatible format.

Efficient conversion of numbers from database floating point format to binary integer format

Approaches are described to improve database performance by implementing a RLE decompression function at a low level within a general-purpose processor or an external block. Specifically, embodiments of a hardware implementation of an instruction for RLE decompression are disclosed. The described approaches improve performance by supporting the RLE decompression function within a processor and/or external block. Specifically, a RLE decompression hardware implementation is disclosed that produces a 64-bit RLE decompression result, with an example embodiment performing the task in two pipelined execution stages with a throughput of one per cycle. According to embodiments, hardware organization of narrow-width shifters operating in parallel, controlled by computed shift counts, is used to perform the decompression. Because of the decreased time required to perform RLE decompression according to embodiments, the performance of tasks that use embodiments described herein for decompression of run-length encoded data is made more efficient.

Run-length encoding decompression

Embodiments of a processor are disclosed for performing arithmetic operations on a machine independent number format. The processor may include a floating point unit, and a number unit. The number format may include a sign/exponent block, a length block, and multiple mantissa digits. The number unit may be configured to perform an operation on two operands by converting the digit format of each mantissa digit of each operand, to perform the operation using the converted mantissa digits, and then to convert each mantissa digit of the result of the operation back into the original digit format.

Floating point unit with support for variable length numbers

Embodiments of a processor are disclosed for performing arithmetic operations on variable-length and fixed-length machine independent numbers. The processor may include a floating point unit, and a logic circuit. The number unit may be configured to receive an operation, and first and second operands. Each of the first and second operands may include a sign byte, and multiple mantissa bytes, and may be processed in response to a determination that the operands are fixed-length numbers. The logic circuit may be further configured to perform the received operation on the processed first and second operands.

Processing fixed and variable length numbers

A multiplier unit that may be configured to concurrently perform multiple division and square operations is disclosed. The multiplier unit may include multiple stages. Each stage may be configured to perform a corresponding arithmetic operation. Control circuitry coupled to the multiplier unit may be configured to schedule in a given cycle of the plurality of cycles, a respective tasks of a plurality of tasks included in a first operation for execution on a respective stage of the multiple stages. The control circuitry may be further configured to schedule execution of each tasks of a second plurality of tasks included in a second operation during a respective cycle on an unused stage of the multiple stages.

Scheduling multiple operations in a divider unit

A mechanism for handling unfused multiply-add accrued exception bits includes a processor including a floating point unit, a storage, and exception logic. The floating-point unit may be configured to execute an unfused multiply-accumulate instruction defined with the instruction set architecture (ISA). The unfused multiply-accumulate instruction may include a multiply sub-operation and an accumulate sub-operation. The storage may be configured to maintain floating-point exception state information. The exception logic may be configured to capture the floating-point exception state after completion of the multiply sub-operation and prior to completion of the accumulate sub-operation, for example, and to update the storage to reflect the floating-point exception state.

Mechanism for handling unfused multiply-accumulate accrued exception bits in a processor

Systems and methods for providing single cycle movement of data between a floating-point register file (FRF) and a general purpose or integer register file (IRF) of a microprocessor system are provided. The system may include an integer execution unit operative to execute instructions with single cycle latency, a floating-point execution unit, a working register file (WRF), an FRF, and an IRF. To achieve the single cycle movement functionality, the integer execution unit may physically own the WRF, IRF, and FRF, and may monitor and control any dependencies between them. Thus, since the integer execution unit has direct read access to both the IRF and the FRF, data may be moved between the two register files using the single cycle operation of the integer execution unit, without the need to store and load the data from memory.

Single cycle data movement between general purpose and floating-point registers

A refrigerator having a door that includes a liquid dispensing system. A gas cylinder mounted on the refrigerator provides regulated gas flow to ports on the dispensing system. A bottle with a dispense head attached then can have liquid displaced by utilization of a valve component of the dispense head.

Refrigerator door wine dispenser

Techniques are disclosed relating to integrated circuits that include hardware support for divide and/or square root operations. In one embodiment, an integrated circuit is disclosed that includes a division unit that, in turn, includes a normalization circuit and a plurality of divide engines. The normalization circuit is configured to normalize a set of operands. Each divide engine is configured to operate on a respective normalized set of operands received from the normalization circuit. In some embodiments, the integrated circuit includes a scheduler unit configured to select instructions for issuance to a plurality of execution units including the division unit. The scheduler unit is further configured to maintain a counter indicative of a number of instructions currently being operated on by the division unit, and to determine, based on the counter whether to schedule subsequent instructions for issuance to the division unit.

Division unit with normalization circuit and plural divide engines for receiving instructions when divide engine availability is indicated

A fluid dispense head is removably joined to a bottle, such as a wine bottle, or similar container, by having a hollow cylinder extend into the bottle and on one end sealed to a neck of the bottle with an annular gasket and on an opposite end joined to the dispense head. A nut on opposite end of the hollow cylinder limits entry of the cylinder into the bottle. When the nut is turned relative to the cylinder, the gasket seal is broken and the dispense head can be removed from the bottle. A set of annular gaskets of different diameters may be provided for bottles of different neck sizes.

Liquid dispensing head forcibly detachable from bottle or container

Implementing an unfused multiply-add instruction within a fused multiply-add pipeline. The system may include an aligner having an input for receiving an addition term, a multiplier tree having two inputs for receiving a first value and a second value for multiplication, and a first carry save adder (CSA), wherein the first CSA may receive partial products from the multiplier tree and an aligned addition term from the aligner. The system may include a fused/unfused multiply add (FUMA) block which may receive the first partial product, the second partial product, and the aligned addition term, wherein the first partial product and the second partial product are not truncated. The FUMA block may perform an unfused multiply add operation or a fused multiply add operation using the first partial product, the second partial product, and the aligned addition term, e.g., depending on an opcode or mode bit.

Processor pipeline which implements fused and unfused multiply-add instructions

A pipelined circuit for performing a divide operation on small operand sizes. The circuit includes a plurality of stages connected together in a series to perform a subtractive divide algorithm based on iterative subtractions and shifts. Each stage computes two quotient bits and outputs a partial remainder value to the next stage in the series. The first and last stages utilize a radix-4 serial architecture with edge modifications to increase efficiency. The intermediate stages utilize a radix-4 parallel architecture. The divide architecture is pipelined such that input operands can be applied to the divider on each clock cycle.

Pipelined divide circuit for small operand sizes

Growing community of inventors

Austin, TX, United States of America

Jeffrey S Brooks