Lenovo (singapore) Pte. Ltd.

International Business Machines Corporation

Globalfoundries Inc.

Jeffrey Ross Hamilton

Alfredo Aldereguia

Clifton Ehrich Kerr

Grace Ann Richter

Ross Lee Mickens

Michael DeCesaris

Markesha F Parker

Pravin S Patel

James Joseph Parsonese

Douglas R Oliver

Brian A Baker

Fred Allison Bower, Iii

Caihong Zhang

Patrick Leo Caporale

Sumanta Kumar Bahali

Peter Robert Seidel

Jack P Wong

Juan Q Hernandez

Melba I Lopez

Brian E Bigelow

Keith T Adams

Connor B Reed

Logan S Gabriel

Jason Allen Browne

Mike Yubo Zhu

Jimmy X Tang

Troy S Voytko

Ann Richter

Jonathan B Russell

Mark J Staley

Xiao Dong Du

Shared memory workloads using existing network fabrics, including: presenting, by a Memory Mapped Input/Output (MMIO) translator, memory of the MMIO translator as a portion of a memory space of a host; receiving, by the MMIO translator, a first interrupt from an input/output (I/O) adapter; and storing, by the MMIO translator, without sending the first interrupt to an operating system, data associated with the first interrupt from the I/O adapter into the memory of the MMIO translator.

Shared memory workloads using existing network fabrics

Topology discovery between compute nodes and interconnect switches including creating, on an interconnect switch, a virtual topology discovery device for a first port, wherein the interconnect switch is coupled to a compute node via the first port, and wherein the virtual topology discovery device comprises a port identifier for the first port; mapping the virtual topology discovery device to the first port; receiving an inventory request from the compute node via the first port; routing the inventory request to the virtual topology discovery device for the first port; and sending, from the virtual topology discovery device for the first port, the port identifier to the compute node.

Topology discovery between compute nodes and interconnect switches

Modifying resources for composed systems based on resource models including receiving a workload for execution on a composed system; extracting workload characteristics from the workload; matching the workload characteristics to a resource model, wherein the resource model comprises an initial configuration of compute elements for the composed system and a configuration modification to the initial configuration of the compute elements as the workload executes; composing the composed system using the initial configuration of compute elements described by the resource model, wherein the composed system comprises a subset of compute elements from a resource pool of compute elements; and executing, based on the resource model, the workload using the composed system, including modifying the initial configuration of the compute elements according to the resource model.

Modifying resources for composed systems based on resource models

Mobile device integration with a virtual reality environment may include: determining a location of a mobile device relative to a head-mounted display displaying a virtual environment; receiving a video stream mirroring a display of the mobile device; rendering, in the virtual environment, based on the location of the mobile device relative to the head-mounted display, a representation of the mobile device comprising the video stream; and outputting, to the head-mounted display, a rendering of the virtual environment comprising the representation of the mobile device.

Mobile device integration with a virtual reality environment

An apparatus for memory management a high-speed fabric controller and a memory controller connected between a high-speed memory and a processor. The memory controller is configured to control processor access to the high-speed memory over a memory bus between the processor and the high-speed memory. The apparatus includes a high-speed data connection between the memory controller and the high-speed fabric controller and a data connection between a tier of persistent data storage and the high-speed fabric controller. The high-speed fabric controller is configured to control data transfers between the tier of persistent data storage over and the high-speed memory independent of the processor.

Controlling data transfers between a tier of persistent data storage and processor memory with a high-speed fabric controller

Storage devices are connected to a Peripheral Component Interconnect Express (PCIe) switch and form an input/output virtualization (IOV) replication cluster that can be exposed to a host processor via hardware root complex interconnecting the PCIe switch to the host processor. When a failed storage device is replaced with a new storage device, the new storage device can initiate a virtual root complex that connects to those storage devices containing data that was replicated on the failed storage device, to receive and copy the data on the new storage device. This replication process does not have to involve the hardware root complex or the host processor.

Replacement of storage device within IOV replication cluster connected to PCI-e switch

Flexible display systems and methods for controlling and operating the same are disclosed herein. According to an aspect, a display system is provided. The display system comprises a display that is configured to be shaped in one of a first shape and a second shape, the first shape and the second shape being different shapes. The display system further comprises electromagnets attached to the display and oriented such that when the electromagnets are actuated, the display is held in the first shape.

Flexible display systems and methods for controlling and operating the same

Address verification on a bus, the bus connecting a plurality of receiving bus nodes and one or more sending bus nodes, the bus providing communication among the bus nodes, including: receiving, by a receiving bus node over the bus, a parity signal and an address signal, the address signal identifying an address of a target receiving bus node; determining, by the receiving bus node, whether the address of the target receiving bus node matches an address of the receiving bus node; responsive to determining that the address of the target receiving bus node matches the address of the receiving bus node, determining, by the receiving bus node, whether the parity signal is an expected parity signal; and responsive to determining that the parity signal is not the expected parity signal, suppressing, by the receiving bus node, an acknowledgment of receipt of the address signal.

Address verification on a bus

Systems and methods for determining an operational condition of a capacitor package are disclosed. According to an aspect, a system may include a capacitor package including a dielectric material operatively connected between a first terminal and a second terminal. The system may include a Zener diode being operatively connected with its cathode at a third terminal and its anode at the second terminal. The system may also include a test pin being conductively connected to the third terminal. The system may also include a testing module configured to receive an electrical output from the test pin. The testing module may also be configured to determine an operational condition of the capacitor package based on the electrical output. The testing module may further be configured to present the operational condition of the capacitor package.

Systems and methods for determining an operational condition of a capacitor package

Methods, systems, and computer program products for backup memory administration are provided. Embodiments include storing in an active memory device, by a memory backup controller, blocks of computer data received from random access memory; recording in a change log, by the memory backup controller, identifications of each block of computer data that is stored in the active memory device; detecting, by the memory backup controller, a backup trigger event; and responsive to the detecting of the backup trigger event: copying, by the memory backup controller, from the active memory device, to a backup memory device, the blocks of data identified in the change log; and clearing, by the memory backup controller, the change log.

Backup memory administration using an active memory device and a backup memory device

A chassis includes a base, a lid, and air baffles disposed within the base. The lid slidably engages opposing base side walls and slides between secured and unsecured positions. In one embodiment, a mechanical latch attaches to the lid and has a spring-biased latch arm for selectively locking the lid to the base and a latch hook for selectively locking the air baffle to the lid, wherein depressing the mechanical latch releases the lid from the base and physically separating the lid from the base causes the latch hook to secure the air baffle for removing the air baffle along with the lid. In another embodiment, a first magnet is attached to the lid and a second magnet is attached to the air baffle, wherein sliding the lid to the unsecured position aligns the first and second magnets and magnetically couples the air baffle to the lid.

Compute chassis having a lid that secures and removes air baffles

Recommending preferred ringer settings for a mobile communications device, including: receiving, from one or more mobile communications devices, location information identifying a location of the mobile communications device; receiving, from one or more mobile communications devices, ringer setting information identifying a ringer setting of the mobile communications device; identifying one or more location zones; and determining, in dependence upon the location information and the ringer setting information, preferred ringer settings for each of the one or more location zones.

Recommending preferred ringer settings for a mobile communications device

Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit ('CPU') sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, performance characteristics associated with each available CPU, the performance characteristics associated with each available CPU including information describing computing devices such as memory devices, input/output ('I/O) devices, and other downstream devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the performance characteristics associated with each available CPU and a predetermined performance policy, a target CPU to utilize as a boot CPU.

Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit ('CPU') sockets

Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit ('CPU') sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, error characteristics associated with each available CPU, wherein the error characteristics associated with each available CPU include error information for computing devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the error characteristics associated with each available CPU and a predetermined error tolerance policy, a target CPU to utilize as a boot CPU.

Growing community of inventors

Pittsboro, NC, United States of America

Jeffrey Ross Hamilton