Apple Inc.

Jeffrey R Wilcox

Manu Gulati

Joshua P De Cesare

Ian P Shaeffer

Farid Nemati

Sukalpa Biswas

Michael J Smith

Joseph Sokol, Jr

Bernard Joseph Semeria

Timothy R Paaske

Jonathan Jay Andrews

Pierre-Olivier J Martel

Andrew D Myrick

Tristan F Schaap

Hardik K Doshi

Xeno S Kovah

Corey T Kallenberg

Nikolaj Schlej

Kevin H Alderfer

Robert W Hill

Robert L Ridenour

Ezekiel T Runyon

Reese A Schreiber

Collin L Pieper

Carlos M Calderon

In one embodiment, a system includes a non-volatile memory that may serve as both the main memory system and the backing store (or persistent storage). In some embodiments, the non-volatile memory is divided into a main memory portion and a persistent portion. Data in the main memory operation may be encrypted using one or more first keys, and data in the persistent portion may be encrypted using one or more second keys, in an embodiment. The volatile behavior of main memory may be implemented by discarding the one or more first keys in a power down event or other event that indicates a loss of main memory data, while the one or more second keys may be retained. In one embodiment, the physical address space of the non-volatile memory may be a mapping from a second physical address space that is used within the system.

Unified addressable memory

An exemplary computer console can generate one or more video streams having image data relating to an image or a series of images, also referred to as video, to be presented by an electronic display device. The exemplary computer console can provide the one or more video streams to the electronic display device over one or more transport streams. The exemplary computer console can effectively throttle a video stream bitrate of the one or more video streams to be less than of the standard defined transport stream bitrate of the one or more transport streams to allow the transport of the one or more video streams over the one or more transport streams.

Computer console for throttling the video bitrate of video streams to interface with an electronic device

A method and apparatus for performing a secure boot of a computer system is disclosed. A computer system according to the disclosure includes an auxiliary processor and a main processor. The boot process includes initially booting the auxiliary processor. The auxiliary processor includes a non-volatile memory storing boot code for the main processor. The auxiliary processor may perform a verification of the boot code. Subsequent to verifying the boot code, the main processor may be released from a reset state. Once the main processor is no longer in the reset state, the boot code may be provided thereto. Thereafter, the boot procedure may continue with the main processor executing the boot code.

Method and apparatus for secure system boot

This application relates to techniques that adjust the sleep states of a computing device based on user proximity detection procedures. The technique includes detecting a first pattern, using a first subset of sensors of one or more sensors coupled to the computing device, to determine if the object is proximate to the computing device. Provided the first pattern is not indicative of the object being proximate to the computing device, the technique detects a second pattern, using a second subset of sensors of the one or more sensors, to determine if the object is proximate to the computing device. Furthermore, provided either the first pattern or the second pattern is indicative of the object being proximate to the computing device and provided a first portion of a computer system within the computing device is operating within a low-power sleep state, the technique causes the first portion to enter into a high-power sleep state.

Techniques for adjusting computing device sleep states using onboard sensors and learned user behaviors

Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuity of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).

Secure circuit control to disable circuitry

In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

Storing address of spare in failed memory location

Techniques are disclosed in which a secure circuit controls a gating circuit to enable or disable other circuitry of a device (e.g., one or more input sensors). For example, the gating circuit may be a power gating circuit and the secure circuit may be configured to disable power to an input sensor in certain situations. As another example, the gating circuit may be a clock gating circuit and the secure circuit may be configured to disable the clock to an input sensor. As yet another example, the gating circuit may be configured to gate a control bus and the secure circuit may be configured to disable control signals to an input sensor. In some embodiments, hardware resources included in or controlled by the secure circuit are not accessible by other elements of the device, other than by sending requests to a predetermined set of memory locations (e.g., a secure mailbox).

A method and apparatus for protecting boot variables is disclosed. A computer system includes a main processor and an auxiliary processor. The auxiliary processor includes a non-volatile memory that stores variables associated with boot code that is also stored thereon. The main processor may send a request to the auxiliary processor to alter one of the variables stored in the non-volatile memory. Responsive to receiving the request, the auxiliary processor may execute a security policy to determine if the main processor meets the criteria for altering the variable. If the auxiliary processor determines that the main processor meets the criteria, it may grant permission to alter the variable.

Method and apparatus for boot variable protection

In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

Growing community of inventors

San Jose, CA, United States of America

Jeffrey R Wilcox