Texas Instruments Corporation

Jeffrey R Quay

Natarajan Kurian Seshan

Kenneth L Williams

Brian Jason Karguth

Michael J Moody

Sharat C Prasad

Jonathan G Bradley

Jason AT Jones

Laurence RJr Simar

A microprocessor,is described which includes a direct memory access (DMA) circuitry,. DMA,is interconnected with a program memory,and a data memory,and is operational to transfer data to or from these memories. DMA,is interconnected with a peripheral bus,and thereby to various peripherals internal to microprocessor,. DMA,is also interconnected with an external memory interface,and thereby to various external memory circuits and peripherals external to microprocessor,. An auxiliary channel control circuitry,provides DMA transfers by interacting with a peripheral such as host port,which has its own address generation circuitry. DMA,provides frame synchronization for triggering a frame transfer, or group of transfers. DMA,is auto-initialized through registers. DMA action complete pins DMAC,indicate DMA status to external devices. DMA,allows for local variability of transfer rates in a split channel mode of operation by allowing a transmit channel to get ahead of a corresponding receive channel by a preselected number of data words.

Direct memory access controller with split channel transfer capability and FIFO buffering

A network hub and Asynchronous Transfer Mode (ATM) translator system (,) for use in a Local Area Network (LAN)-based communications system is disclosed. The network hub and ATM translator system (,) includes a host controller (,) that serves as the LAN hub, and which interfaces with a translator card (,) which includes a segmentation and reassembly device (,) in connection with SONET receive/transmit circuitry (,) that communicates with a transceiver (,) to transmit and receive ATM packet cells over a communications facility (FO). The translator card (,) also includes a scheduler (,) that includes a heap sort state machine (,) which maintains a sorted list of entries, in a heap fashion, in on-chip parameter memory (,) and off-chip parameter memory (,). The entries include, for each ATM channel, a channel identifier and a timestamp that indicates the time at which the next cell for the channel will be due for transmission. A due comparator (,) compares the timestamp of the root value in the heap (i.e., the channel with the next due cell) to a global time generated by a reference timer (,), and indicates to a source behavior processor (,) in the scheduler (,) that a cell is due for transmission. The scheduler than issues a transmit credit for the cell, and communicates this event with the SAR device (,) to effect the transmission as appropriate.

ATM cell scheduler which uses a heap memory and associates timestamps with each channel

A microprocessor 1 is described which includes a direct memory access (DMA) circuitry 143. DMA 143 is interconnected with a program memory 23 and a data memory 22 and is operational to transfer data to or from these memories. DMA 143 is interconnected with a peripheral bus 110 and thereby to various peripherals internal to microprocessor 1. DMA 143 is also interconnected with an external memory interface 103 and thereby to various external memory circuits and peripherals external to microprocessor 1. An auxiliary channel control circuitry 160 provides DMA transfers by interacting with a peripheral such as host port 150 which has its own address generation circuitry. DMA 143 provides frame synchronization for triggering a frame transfer, or group of transfers. DMA 143 is auto-initialized through registers. DMA action complete pins DMAC0-3 indicate DMA status to external devices. DMA 143 allows for local variability of transfer rates in a split channel mode of operation by allowing a transmit channel to get ahead of a corresponding receive channel by a preselected number of data words.

DMA controller with split channel transfer capability and FIFO buffering

A network hub and Asynchronous Transfer Mode (ATM) translator system (5) for use in a Local Area Network (LAN)-based communications system is disclosed. The network hub and ATM translator system (5) includes a host controller (10) that serves as the LAN hub, and which interfaces with a translator card (15) which includes a segmentation and reassembly device (12) in connection with SONET receive/transmit circuitry (20) that communicates with a transceiver (22) to transmit and receive ATM packet cells over a communications facility (FO). The translator card (15) also includes a scheduler (14) that includes a heap sort state machine (36) which maintains a sorted list of entries, in a heap fashion, in on-chip parameter memory (44) and off-chip parameter memory (18). The entries include, for each ATM channel, a channel identifier and a timestamp that indicates the time at which the next cell for the channel will be due for transmission. A due comparator (40) compares the timestamp of the root value in the heap (i.e., the channel with the next due cell) to a global time generated by a reference timer (38), and indicates to a source behavior processor (24) in the scheduler (14) that a cell is due for transmission. The scheduler than issues a transmit credit for the cell, and communicates this event with the SAR device (12) to effect the transmission as appropriate.

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Royse City, TX, United States of America

Jeffrey R Quay