International Business Machines Corporation

Vegherb, LLC

Fed Corporation

Jeffrey R Marino

Anthony G Topping

Vincent James McGahay

Carlos Juan Sambucetti

Habib Hichri

Bernd E Kastenmeier

Joseph K Ho

Chih-Chao Yang

Lawrence Alfred Clevenger

Cyprian Emeka Uzoh

Theodorus E Standaert

Timothy Joseph Dalton

Alejandro Gabriel Schrott

Eugene John O'Sullivan

Kevin Shawn Petrarca

Andrew Herbert Simon

Richard Paul Volant

Fuad Elias Doany

Yun-Yu Wang

Chandrasekhar Narayan

Kwong Hon Wong

Ravi F Saraf

Gary W Jones

Steven M Zimmerman

Michael Wayne Lane

Ian D Melville

Vlasta A Brusic

Kelly Malone

Matthew S Angyal

Brett H Engel

Larry Clevenger

Peter E Biolsi

Susan K Jones

Yachin Liu

Brian Wayne Herbst

Michael J Costa

Jeffrey A Silvernail

Arthur W Martin

Sanjit Kumar Das

Stanley J Klepeis

R Mark Boysel

Hsiao-Ling Lu

Methods for sealing an organic ILD layer and a metal layer after an etching step. The method includes etching through an ILD layer and leaving a remaining portion of an underlying metal layer cap, maintaining the device in an inert gas, and depositing at least a portion of a liner into the opening to seal the ILD layer and the metal layer. Subsequent processing may include formation of a via by etching through the portion of the liner and the remaining portion of the cap layer, and depositing a metal.

Interlevel dielectric layer and metal layer sealing

A method to selectively metallize polyimide with an all-electroless process.

Means of seeding and metallizing polyimide

An interconnect structure for a semiconductor device includes an organic, low dielectric constant (low-k) dielectric layer formed over a lower metallization level. A via formed is within the low-k dielectric layer, the via connecting a lower metallization line formed in the lower metallization level with an upper metallization line formed in an upper metallization level. The via is surrounded by a structural collar selected from a material having a coefficient of thermal expansion (CTE) so as to protect the via from shearing forces following a thermal expansion of the low-k dielectric layer.

Structure and method for reducing thermo-mechanical stress in stacked vias

In copper backend integrated circuit technology, advanced technology using low-k organic-based interlayer dielectrics have a problem of carbon contamination that dos not occur in circuits using oxide as dielectric. A composite liner layer for the copper lines uses Ti as the bottom layer, which has the property of gettering carbon and other contaminants. The known problem with Ti of reacting with copper to form a high resistivity compound is avoided by adding a layer of TiN, which isolates the Ti and the copper.

Ti liner for copper interconnect with low-k dielectric

The invention provides a simple device for providing vertical support of vegetable plants, thereby eliminating the conventional problems routinely associated with home gardening. In particular, the device provides a maintenance free, vertical support frame assembly of adjustable height to which is attached a mesh netting and supporting stakes, forming an extendable garden trellis. Growing plants may be attached to the gardening trellis, thereby allowing maximum upward growth of the plants while also elevating the plants.

Garden trellis wall system

A support bracket and stake are provided which can be used for edging gardens and lawns or for the formation of retaining walls. Used together, the bracket and stake provide a means to support and anchor lengths of lumber to the ground to create a variety of edging systems. In particular, the stakes provide a means to attach the system securely to the ground surface, while the support bracket has a beam receiving portion to support a variety of different types of lumber frequently used in edging. A mounting column on the support bracket provides a means to secure the support bracket to the stakes such that the support bracket may freely rotate 360&deg; perpendicular to the vertical axis of the stake. The stakes may be vertically engaged one upon and inside the other to provide a raised border system of various height. Where it is desired to vertically engage the stakes, more than one bracket may be secured to the vertical stakes, one bracket on top of the other, so as to support and anchor lengths of lumber, one on top of the other, to form a wall of any desired height.

Raised border system

Trellis bracket

Tee pee leg connector

Raised bed bracket

Field emission devices may include emitter wells formed in a body of dielectric material. A gate conductor may be provided along the upper surface of the dielectric material. A gate hole may be provided in the gate conductor directly above each of the emitter wells. A method for forming the gate holes and emitter wells is disclosed. The method includes the steps of providing a first gate conductor layer on a dielectric layer. A pattern of second gate conductor material may be formed over the first gate conductor layer, said pattern defining gate holes in the second gate conductor material. The gate holes may then be completed and emitter wells formed by etching through the first gate conductor layer and into the dielectric layer using an etch that selectively etches the first gate conductor layer and the dielectric layer, and does not etch substantially the second gate conductor material.

Gate electrode structure for field emission devices and method of making

A field emitter device includes a column conductor, an insulator, and a resistor structure for advantageously limiting current in a field emitter array. A wide column conductor is deposited on an insulating substrate. An insulator is laid over the column conductor. A high resistance layer is placed on the insulator and is physically isolated from the column conductor. The high resistance material may be chromium oxide or 10%-50% wt % Cr+SiO. A group of microtip electron emitters is placed over the high resistance layer. A low resistance strap interconnects the column conductor with the high resistance layer to connect in an electrical series circuit the column conductor, the high resistance layer, and the group of electron emitters. One or more layers of insulator and a gate electrode, all with cavities for the electron emitters, are laid over the high resistance material. One layer of insulator is selected from a group of materials including SiC, SiO, and Si.sub.3 N.sub.4. An anode plate is attached with intermediate space between the anode plate and the microtip electron emitters being evacuated.

Field emitter device with a current limiter structure

A process for electrolessly depositing cobalt-tin alloys with adjustable tin contents from 1 to over 25 atomic percent tin is disclosed. The deposited alloy is useful in the electronics and computer industries for device, chip interconnection and packaging applications. When used for chip interconnection applications, for example, the invention replaces the currently used complicated ball-limiting-metallurgy. The invention may also be used to inhibit hillock formation and electromigration in copper wire structures found in computers and micron dimension electronic devices.

Cobalt-tin alloys and their applications for devices, chip

Growing community of inventors

Fishkill, NY, United States of America

Jeffrey R Marino