Gte Laboratories Incorporated

Jeffrey R Fox

Rob Moolenbeek

Arthur Margolies

Martin L Resnick

Hans G Blank

William D Walsh

Input and output fault monitoring circuits for determining the presence of integrated circuit chip open connections at the input and output pads of each circuit on a chip. The input fault monitoring circuit operates on the principle that if there is no input signal from the input pad throughout the known duty cycle or frequency of the input circuit, a defect, such as an open circuit interconnect, has occurred. The output fault monitoring circuit generates a signal through a dummy circuit connected to the output circuit which has a time delay intermediate that of the output circuit operating into a connected output pad and that of the output circuit when operating into a disconnected pad. Thus, the time of arrival of the dummy circuit signal in relation to that of the actual output signal is used to indicate the presence or absence of a disconnected output pad.

Integrated circuit input-output diagnostic system

An MOS FET inverter driver circuit. A first FET of the depletion type, a resistance formed by a depletion type FET having its gate connected to its drain, and a second FET of the enhancement type are connected in series between a positive voltage source and ground. Third and fourth FET's both of the enhancement type are also connected in series between the voltage source and ground. The gates of the first, second, and fourth FET's are connected directly to an input terminal. The gate of the third FET is connected to the juncture of the resistance FET and the second FET. A capacitance is connected between the juncture of the resistance FET and the first FET and the juncture of the third and fourth FET's, an output terminal is also connected to this juncture. The circuit obtains bootstrap action by virtue of the capacitance to provide high voltage drive to turn the third FET, the output pull-up transistor, on. The direct connection from the input terminal to the gates of the first, second, and fourth FET's further contributes to high speed operation of the circuit.

Driver circuit

A metal-oxide-silicon (MOS) field effect transistor (FET) regenerative differential comparator circuit particularly suited for use in sigma-delta modulation apparatus. The circuit includes two differential amplifier stages followed by a latching amplifier stage. A regenerative latching section of two cross-connected latching FET's is connected to the latching amplifier stage. Each of the latching FET's is connected in series with a separate switching FET. A strobe pulse turns on the two switching FET's enabling the latching FET's. Depending on the relative polarity of the differential voltage produced by the latching amplifier stage, regenerative action drives one of the two latching FET's into heavy conduction thereby producing an appropriate digital output. The first two differential amplifier stages remain enabled during the regenerative action permitting high speed operation.

Comparator circuit

Apparatus for a monitoring and signalling system such as a home health care system includes a plurality of sensors operative to monitor the occurrence of activities performed by an individual in his or her residence and to produce binary coded signals indicative of the occurrence of the monitored activities. Each signal comprises six successive identical messages within a one-second interval, with each message including a binary word identifying the monitoring and signalling system, the particular sensor originating the signal, and the nature of the monitored activity. Each message further includes a preamble and a pair of interwords on opposite sides of the binary word. The apparatus in accordance with the invention includes a microprocessor which operates to repetitively sample each signal originating with a sensor to determine the binary content of the signal and to extract a binary word from a message while rejecting preambles, interwords and 'glitches' (noise) present in the signal. The extracted binary word is then tested as to its satisfaction of predetermined requirements. If the binary word of one message satisfies these requirements, an interval of time is established during which a binary word of the next message is required to be extracted from the next message and also satisfy the predetermined requirements before permitting further processing of the second binary word.

Monitoring and signalling system including apparatus for processing

Electrical power supply for use with apparatus which transmits a predetermined message. When an input signal is received, a source of electrical energy is connected to a power output terminal by turning a switching transistor on. A latching circuit holds the transistor on after termination of the input signal. Elements of the apparatus which are connected to the power output terminal to obtain operating power transmit the predetermined message when the electrical energy is supplied to the terminal. When the transmission is complete, the apparatus produces a termination signal to the latching circuit causing it to turn the switching transistor off and thus disconnect the source of electrical energy from the power output terminal. A delay arrangement prevents the latching circuit from responding to a termination signal for a predetermined period of time after the input signal has terminated, thus preventing inadvertent disconnecting of the source of electrical energy from the power output terminal before the apparatus has had an opportunity to attain full operation.

Electrical power supply apparatus

A logic level converter converts an input signal having first and second voltage levels to an output signal having first and third voltage levels in which the voltage excursion of the output signal is greater than that of the input signal. The converter comprises first and second cross-coupled inverters in which the second inverter provides the output signal and is biased with respect to the first and third voltage levels and in which the first inverter is biased with respect to the third voltage level and the digital input signal. A voltage divider is associated with the first inverter to insure sufficient voltage swing for proper switching of the inverters. The inverters have dissimilar gains to insure that when the inverters are biased at equal voltages, the inverters always assume a predetermined state. The converter is implemented with PMOS field effect transistors and includes capacitors for increasing switching speed.

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Concord, MA, United States of America

Jeffrey R Fox