Micron Technology Incorporated

Micron Electronics, Inc.

Jeffrey R Brown

Joseph M Jeddeloh

Douglas Alan Larson

James W Meyer

Memory system controllers can include a switch and non-volatile memory control circuitry coupled to the switch. The non-volatile memory control circuitry can include a channel control circuit coupled to logical units. The channel control circuitry can be configured to relay an erase command to a first one of the logical units and relay a particular command from the switch to a second one of the logical units while the erase command is being executed on the first one of the plurality of logical units.

Apparatus including memory channel control circuit and related methods for relaying commands to logical units

One embodiment of the present invention provides a system that supports multiple delayed read transactions. The system includes a host bus and a peripheral bus. The system also includes a receiving mechanism that is configured to receive a first request and a pipelined request that originate from the host bus and are directed to the peripheral bus. The first request and the pipelined request are stored in a first buffer and a second buffer. The system additionally includes a sending mechanism that is configured to send the first request to the peripheral bus, so that the first request is processed when the peripheral bus becomes available. If the pipelined request is received and if the pipelined request is a read operation, the sending mechanism is configured to send the pipelined request to the peripheral bus, so that the pipelined request will be processed when the peripheral bus becomes available. The system also includes a retry mechanism that issues a retry request across the host bus that causes both the first request and the pipelined request to be retried at a later time on the host bus so that the host bus can be freed up for other transactions.

Apparatus for supporting multiple delayed read transactions between computer buses

One embodiment of the present invention provides a method that supports multiple delayed read transactions between a host bus and a peripheral bus in a computer system. The method operates by receiving a first request that is a read operation from the host bus that is directed to the peripheral bus. The first request is stored in a first buffer and sent to the peripheral bus, so that the first request will be processed when the peripheral bus becomes available. Next, the system waits to receive a pipelined request that is a read operation from the host bus that is directed to the peripheral bus. If such a pipelined request is received, the system stores the pipelined request in a second buffer, and sends the pipelined request to the peripheral bus, so that the pipelined request will be processed when the peripheral bus becomes available. Next, the system issues a retry request across the host bus. This retry request causes both the first request and the pipelined request to be retried at a later time on the host bus so that the host bus can be freed up for other transactions while the first request and the pipelined request are in process on the peripheral bus. In one embodiment of the present invention, if the first request is a read operation that was previously requested, the system determines if read data from the previous request has been returned by the peripheral bus. If so, the system returns the read data across the host bus to complete the first request. Otherwise, the system issues a retry request across the host bus to cause the first request to be retried at a later time.

Method for supporting multiple delayed read transactions between computer buses

A method and computer readable medium are provided for analyzing the integrity of a sensitivity list for a process statement in a hardware description language file. An example of a hardware description language to which the method can be applied is VHDL. The method compares an actual sensitivity list from a hardware description language file to an expected sensitivity list that includes one or more parameters expected to appear in the actual sensitivity list. In the event the actual sensitivity list deviates from the expected sensitivity list, the integrity of the actual sensitivity lists is compromised. In this case, an advisory can be generated to identify the deviation, and note its location within the hardware description language file. In this manner, the designer can quickly find the defective sensitivity list and correct it prior to simulation. A sensitivity list verification method can significantly reduce the time and effort involved in sensitivity list debugging. Consequently, the designer can devote more time and resources to the design effort and the end objective of producing the subject design. In many cases, reduction of debugging costs will bear significantly on the final cost of the design. At the same time, reduction of debugging time can shorten the design cycle.

Verification of sensitivity list integrity in a hardware description language file

One embodiment of the present invention provides a method for designing a circuit that limits the impact of design changes within a module of a circuit to the characteristics of signals flowing between modules of the circuit. This method operates by dividing the circuit into a plurality of circuit modules, and defining a plurality of interface modules located between the plurality of circuit modules. These interface modules include drivers coupled between upstream circuit module outputs and downstream circuit module inputs, so as to isolate the downstream circuit module inputs from the upstream circuit module outputs. Next, the circuit modules and interface modules are designed, and a synthesized circuit is ultimately generated from the designs. This synthesized circuit is then verified for characteristics such as timing. If it fails to verify, design changes are made. In one embodiment, these design changes include: re-specifying constraints for modules, re-generating designs for modules, and re-dividing the circuit into modules. By locating drivers within separate interface modules, the drive strengths of the drivers can be more easily specified. Furthermore, by locating the drivers at particular positions within an interface module, the signals flowing through the drivers can be guided to flow in such a way as to route signals along shorter, more optimal pathways between modules.

Inter-module buffer determination methodology for ASIC synthesis

A method and computer readable medium are provided for analyzing the integrity of a port list for a component and instantiated modules in a hardware description language file. An example of a hardware description language to which the method and the computer readable medium can be applied is VHDL. The method compares the port lists for a component and associated modules. In the event the component port list and module port list differ, an advisory can be generated to indicated a potential error. The advisory can identify the deviation, and note its location within the hardware description language file. In this manner, the designer can quickly find the port list errors and correct them prior to simulation. Such a port list verification method can significantly reduce the time and effort involved in port list debugging. Consequently, the designer can devote more time and resources to the design effort and the end objective of producing the subject design. In many cases, reduction of debugging costs will bear significantly on the final cost of the design. At the same time, reduction of debugging time can shorten the design cycle.

Verification of port list integrity in a hardware description language file

Inserting buffers between modules to limit changes to inter-module

One embodiment of the present invention can be characterized as a method for designing a circuit that facilitates sharing of design parameters between separately designed modules of the circuit. The method includes receiving module information, including parameters relating to design of a module of the circuit, and storing the module information in a database. The method also includes retrieving the module information from the database, and generating automatically a constraint file from the module information. In one embodiment, this constraint file includes constraints in a format suitable for use by a synthesis tool to synthesize circuitry for the module.

Inter-module data management methodology for circuit synthesis

A computer system has a system memory, cache memory, system controller that process memory transactions. The system controller transmits a memory request to the system memory without waiting for the cache memory to be snooped to determine whether the cache memory stores information in an address corresponding to a selected address of the system memory. The system controller may transmit a snoop request to the cache memory concurrently with or after the memory request is transmitted to the system memory. The system controller may have a control switch that uses a first pathway for the memory request and a second pathway for the snoop request so that the snoop and memory requests can be transmitted simultaneously.

Apparatus for performing a low latency memory read with concurrent snoop

A method processes memory transactions in a computer system having a system memory and a cache memory. The method transmits a memory request to the system memory without waiting for the cache memory to be snooped to determine whether the cache memory stores information in an address corresponding to a selected address of the system memory. The method may transmit a snoop request to the cache memory concurrently with or after the memory request is transmitted to the system memory. The method may be implemented using a system controller having a control switch that uses a first pathway for the memory request and a second pathway for the snoop request so that the snoop and memory requests can be transmitted simultaneously.

Growing community of inventors

Minnetonka, MN, United States of America

Jeffrey R Brown