Motorola Corporation

Jeffrey Pidge Rupley, Ii

Bradley Gene Burgess

Marvin A Denman

David C Holloway

Paul C Rossbach

Albert R Kennedy

A branch prediction unit apparatus and method uses an instruction buffer ( ), a completion unit ( ), and a branch prediction unit (BPU) ( ). The instruction buffer ( ) and/or the completion unit ( ) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers ( ). The SID bits are used to associate the pending and executing instructions in the units ( and ) into instruction streams related to predicted branches located in the buffers ( ). The SID bits as well as age bits associated with the buffers ( ) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.

Apparatus and method for predicting multiple branches and performing out-of-order branch resolution

When a request to branch to an address stored in a return memory location (440) occurs, a busy bit is used to determine whether the return memory location (440) contains updated information. When the information is not updated, a predicted address is provided to the prediction verifier (460) by the link stack (410). Once the busy bit is valid, the prediction verifier (460) determines if a proper prediction was made. When an improper prediction was made, the update portion (415) of the link stack (410) based on information from the comparator (425) determines if a value stored in the link stack (410) matches the value stored in the return memory location (440). The link stack (410) is synchronized based upon a favorable comparison indicating the return memory location value matches a value in the link stack. If a match is not found, the predicted address is placed back on the link stack or alternatively the link stack is cleared.

Data processing system having a synchronizing link stack and method

A branch prediction unit apparatus and method uses an instruction buffer (20), a completion unit (24), and a branch prediction unit (BPU) (28). The instruction buffer (20) and/or the completion unit (24) contain a plurality of instruction entries that contain valid bits and stream identifier (SID) bits. The branch prediction unit contains a plurality of branch prediction buffers (28a-28c). The SID bits are used to associate the pending and executing instructions in the units (20 and 24) into instruction streams related to predicted branches located in the buffers (28a-28c). The SID bits as well as age bits associated with the buffers (28a-28c) are used to perform efficient branch prediction, branch resolution/retirement, and branch misprediction recovery.

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Austin, TX, United States of America

Jeffrey Pidge Rupley, Ii