Hewlett-packard Development Company, L.p.

Hewlett-packard Company

Jeffrey Paul Witte

Don D Josephson

Daniel J Dixon

Quanhong Zhu

Rex Petersen

Jon Eric Josephson

Adam Stuart Block

A system and method for measuring fault coverage in an integrated circuit (IC) using a stuck-at fault model is disclosed. The system includes a Device Under Test (DUT) assembly having the IC that includes at least one node, a probe and a test pattern generator and interface system. The DUT's nodes are operable to be stimulated to a stuck-at fault state when stimulated by a certain frequency of electromagnetic (EM) radiation, which fault state is operable to be discovered by a suitable test vector set.

System and method for measuring fault coverage in an integrated circuit

Two synchronizing flip-flops synchronize the transitions of a slow clock to a fast clock. The state of a version of the synchronized slow clock is stored by a last-state flip-flop that is clocked on an edge of the fast clock. The last-state flip-flop is compared by logic to a version of the synchronized slow clock to produce a pulse with a width determined by either a phase of the fast clock or a cycle of the fast clock.

Clock pulse width control circuit

A method and system for inserting in-place interconnect repeaters along the paths of interconnects of an integrated circuit is presented. The integrated circuit includes an interconnect layer on which an interconnect is routed, a silicon layer in which repeaters are implemented, and zero or more intervening layers. In accordance with the invention, reserved metal areas are defined on each intervening layer that resides between the interconnect layer and the repeater layer. Each interconnect net that requires a repeater for performance reasons is assigned to a repeater location. A repeater buffer is inserted at the assigned repeater locations. The interconnect net is cut into first and second subnets, which are then respectively connected through the reserved metal areas of the intervening layers to the respective input and output port of the repeater buffer.

In-place method for inserting repeater buffers in an integrated circuit

A method and system for performing in-place insertion of interconnect repeaters in an integrated circuit is presented. The integrated circuit comprises a silicon layer and at least one interconnect layer layered over said silicon layer. Metal tracks are reserved on each of the interconnect layers in predefined repeater areas. The interconnects are then routed to pass over the pre-defined repeater areas. For each interconnect, a set of optimal constrained repeater locations are calculated, as defined by the optimal number and locations of repeaters along the interconnect route and as constrained by a set of legal repeater locations associated with the interconnect and which will result in acceptable timing criteria. For each calculated optimal constrained repeater location, a repeater is stitched in-place through the reserved metal tracks of the intervening layers.

In-place repeater insertion methodology for over-the-block routed integrated circuits

A method and system for managing metal resources in the physical design of integrated circuits is presented. Percent metal usage is allocated for intra-block routing use by each functional block. Power and clock grids are established. Block designers coordinate the locations of signal ports of the blocks so as to avoid blocking any inter-block signals, areas of metal are then reserved for ports and intra-block signals. The inter-block signals are then pre-routed, avoiding the power grid, clock grid, and reserved intra-block routing metal. If any problem nets emerge from the pre-routing, better port locations and sub-block placement within the respective blocks are determined and the process is repeated.

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Ft. Collins, CO, United States of America

Jeffrey Paul Witte