Growing community of inventors

Poughkeepsie, NY, United States of America

Jeffrey Paul Soreff

Average Co-Inventor Count = 4.10

ph-index = 6

The patent ph-index is calculated by counting the number of publications for which an author has been cited by other authors at least that same number of times.

Forward Citations = 122

Jeffrey Paul SoreffVasant B Rao (9 patents)Jeffrey Paul SoreffDavid James Hathaway (6 patents)Jeffrey Paul SoreffJames Douglas Warnock (5 patents)Jeffrey Paul SoreffXin Zhao (3 patents)Jeffrey Paul SoreffJeffrey G Hemmett (3 patents)Jeffrey Paul SoreffRobert J Allen (3 patents)Jeffrey Paul SoreffRavichander Ledalla (3 patents)Jeffrey Paul SoreffYanai Danan (3 patents)Jeffrey Paul SoreffEric A Foreman (2 patents)Jeffrey Paul SoreffPeter Anton Habitz (2 patents)Jeffrey Paul SoreffKerim Kalafala (2 patents)Jeffrey Paul SoreffDieter F Wendel (2 patents)Jeffrey Paul SoreffErwin Behnen (2 patents)Jeffrey Paul SoreffDavid Wells Winston (2 patents)Jeffrey Paul SoreffBarry Lee Dorfman (2 patents)Jeffrey Paul SoreffFred Lei Yang (2 patents)Jeffrey Paul SoreffJun Zhou (1 patent)Jeffrey Paul SoreffRonald Dennis Rose (1 patent)Jeffrey Paul SoreffThomas Edward Rosser (1 patent)Jeffrey Paul SoreffPatrick M Williams (1 patent)Jeffrey Paul SoreffPhilip George Shephard, Iii (1 patent)Jeffrey Paul SoreffDaniel Lawrence Ostapko (1 patent)Jeffrey Paul SoreffWilm Ernst Donath (1 patent)Jeffrey Paul SoreffJin-Fuw Lee (1 patent)Jeffrey Paul SoreffCindy ShuiKing Washburn (1 patent)Jeffrey Paul SoreffNeil R Vanderschaaf (1 patent)Jeffrey Paul SoreffSang Y Lee (1 patent)Jeffrey Paul SoreffAli Sadigh (1 patent)Jeffrey Paul SoreffRobert B Hitchcock (1 patent)Jeffrey Paul SoreffChak-Kuen Wong (1 patent)Jeffrey Paul SoreffBhavana Agrawal (1 patent)Jeffrey Paul SoreffJeffrey Paul Soreff (19 patents)Vasant B RaoVasant B Rao (24 patents)David James HathawayDavid James Hathaway (126 patents)James Douglas WarnockJames Douglas Warnock (66 patents)Xin ZhaoXin Zhao (72 patents)Jeffrey G HemmettJeffrey G Hemmett (62 patents)Robert J AllenRobert J Allen (44 patents)Ravichander LedallaRavichander Ledalla (7 patents)Yanai DananYanai Danan (5 patents)Eric A ForemanEric A Foreman (91 patents)Peter Anton HabitzPeter Anton Habitz (82 patents)Kerim KalafalaKerim Kalafala (80 patents)Dieter F WendelDieter F Wendel (73 patents)Erwin BehnenErwin Behnen (11 patents)David Wells WinstonDavid Wells Winston (9 patents)Barry Lee DorfmanBarry Lee Dorfman (7 patents)Fred Lei YangFred Lei Yang (2 patents)Jun ZhouJun Zhou (131 patents)Ronald Dennis RoseRonald Dennis Rose (32 patents)Thomas Edward RosserThomas Edward Rosser (22 patents)Patrick M WilliamsPatrick M Williams (15 patents)Philip George Shephard, IiiPhilip George Shephard, Iii (14 patents)Daniel Lawrence OstapkoDaniel Lawrence Ostapko (13 patents)Wilm Ernst DonathWilm Ernst Donath (11 patents)Jin-Fuw LeeJin-Fuw Lee (9 patents)Cindy ShuiKing WashburnCindy ShuiKing Washburn (7 patents)Neil R VanderschaafNeil R Vanderschaaf (5 patents)Sang Y LeeSang Y Lee (4 patents)Ali SadighAli Sadigh (3 patents)Robert B HitchcockRobert B Hitchcock (2 patents)Chak-Kuen WongChak-Kuen Wong (1 patent)Bhavana AgrawalBhavana Agrawal (1 patent)
..
Inventor’s number of patents
..
Strength of working relationships

Company Filing History:

1. International Business Machines Corporation (19 from 164,108 patents)


19 patents:

1. 10949593 - Model order reduction in transistor level timing

2. 10394986 - Model order reduction in transistor level timing

3. 10031988 - Model order reduction in transistor level timing

4. 8655634 - Modeling loading effects of a transistor network

5. 8607176 - Delay model construction in the presence of multiple input switching events

6. 8201120 - Timing point selection for a static timing analysis in the presence of interconnect electrical elements

7. 8141014 - System and method for common history pessimism relief during static timing analysis

8. 8108816 - Device history based delay variation adjustment during static timing analysis

9. 7870515 - System and method for improved hierarchical analysis of electronic circuits

10. 7643981 - Pulse waveform timing in EinsTLT templates

11. 7552040 - Method and system for modeling logical circuit blocks including transistor gate capacitance loading effects

12. 7325210 - Hybrid linear wire model approach to tuning transistor widths of circuits with RC interconnect

13. 7225419 - Methods for modeling latch transparency

14. 7191419 - Method of timing model abstraction for circuits containing simultaneously switching internal signals

15. 7080335 - Methods for modeling latch transparency

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