International Business Machines Corporation

Jeffrey Paul Kubala

Charles W Gainey, Jr

Donald W Schmidt

Mark S Farrell

Damian Leo Osisek

Dan F Greiner

Timothy John Slegel

Jonathan D Bradbury

Fadi Y Busaba

Lisa Cranton Heller

Robert R Rogers

Harry M Yudenfriend

Leslie W Wyman

Bernard R Pierce

Jeffrey Mark Nick

Frank William Brice

James H Mulder

Kenneth J Oakes

Muruganandam Somasundaram

Charles E Shapley

Jerry A Moody

Tan Lu

Peter Bergersen Yocom

Janet R Easton

Marten J Halma

Hans-Helge Lehmann

Ira Glenn Siegel

John S Trotter

Jonathan David Bradbury

Fadi Yusuf Busaba

Christian Jacobi

Steven G Glassen

Beth A Glendening

Eugene P Hefferon

Scott M Carlson

Allan Samuel Meritt

Peter Jeremy Relson

Roger E Hough

Gary Stuart Puchkoff

Greg A Dyck

Donald Fred Ault

Gary M King

Jose R Castano

Robert J Maddison

Mark A Wisniewski

Dale Francis Riedy, Jr

Gustav E Sittmann, Iii

William J Rooney

Carol B Hernandez

Kenneth M Trowell

Seth E Lederer

Hunter J Kauffman

John Charles Nagy

Norman Ehsan Shafa

Ugochukwu Njoku-Charles

James Edward Bostick

John R Flanagan

Jerry Wayne Stevens

David Harold Surman

Paul Gregory Greenstein

Donna N Dillenberger

Frank Siegfried Lehnert

Bernd Nerz

John Ted Rodell

Steven N Goss

Christine Axnix

Joseph L Temple, Iii

Timothy J Siegel

Thomas B Mathias

John Andrew Aiken, Jr

Catherine Krueger Eilert

Wendell W Wilkinson

Juergen Probst

Ambrose A Verdibello, Jr

David E Stucki

David E Whitney

Alberto Poggesi

Jonel George

Wolfgang Eckert

Suzanne M John

Robert A Smith

Michael Burrill Phillips

Jeffrey G Chan

Roberto J Sanchez

David W Hollar

Heinrich K Lindner

Steven Messinger

Karen Udy Chang

Daniel A Kaberon

Richard A Bellin, Jr

Karen M Noonan

Rodney Allen Paul

Klaus-Jurgen Kuebl

Andreas Muehlbach

Carl J Hollenback

Ugochukwo Njoku-Charles

Michael G Melendy

Marcus Eder

Charles (deceased) Gainey

Pierce Bernard

In an approach for managing physical processor usage of a shared memory buffer, a processor receives a request for memory. A processor receives a request for memory from a process running on a physical processor. A processor determines whether the request for memory is less than or equal to a pre-determined threshold, wherein the pre-determined threshold is based on characteristics of a server on which the physical processor resides, needs of the server, and a frequency of requests of each memory size. Responsive to determining the request for memory is greater than the pre-determined threshold, a processor identifies a node on which the physical processor resides. A processor identifies a memory buffer of a set of memory buffers allocated to the node on which the physical processor resides. A processor allocates the memory buffer.

Managing memory buffer allocation in multi-processor system

In an approach for isolating physical processors during optimization of virtual machine placement, a server is provided comprising a plurality of containers and a plurality of physical processors. A processor builds a set of bit masks for each type of physical processor required for a logical partition. A processor builds a set of solution spaces based on the plurality of containers and an amount of each type of container of the plurality of containers. A processor completes a combinatorial search of the set of bitmasks and the set of solution spaces. A processor identifies a solution space of the set of solution spaces for the logical partition. The physical and logical configuration of the server is changed based on the solution space for the first logical partition.

Isolating physical processors during optimization of VM placement

A system and method of executing a plurality of threads, including a first thread and a set of remaining threads, on a computer processor core. The system and method includes determining that a start interpretive execution exit condition exists; determining that the computer processor core is within a grace period; and entering by the first thread a start interpretive execution exit sync loop without signaling to any of the set of remaining threads. In turn, the first thread remains in the start interpretive execution exit sync loop until the grace period expires or each of the remaining threads enters a corresponding start interpretive execution exit sync loop.

Efficiency for coordinated start interpretive execution exit for a multithreaded processor

Embodiments of the present invention are directed to a computer-implemented method for process management. The method includes assigning a drawer and a physical processor to each element of a first ready queue pointer array, wherein each element of the first ready queue pointer array is configured to point to a memory address of a ready queue header. The method further includes assigning the drawer and the physical processor to each element of a second ready queue pointer array, wherein each element of the second ready queue pointer array is configured to point to the same ready queue header as a respective element of the first ready queue pointer array. The method further includes detecting that either a physical processor has become unavailable to process executable instructions or that a ready queue is empty. The method further includes allocating an available physical processor and a ready queue with executable instructions.

Indirection-based process management

A system and method of implementing a wait state for a plurality of threads executing on a computer processor core of the processor. The processor is configured to execute instruction streams by the plurality of threads, wherein the plurality of threads includes a first thread and a set of remaining threads and determine that the first thread has entered a first wait state loop. The processor is also configured to determine that any of the set of remaining threads has not entered a corresponding wait state loop and remain by the first thread in the first wait state loop until each of the set of remaining threads has entered the corresponding wait state loop.

Described herein are technical features for freeing a buffer used during execution of a work-item by a multiprocessor. An example method includes identifying a first processing unit that assigned the buffer to the work-item, in response to a request from a second processing unit to free the buffer. The computer-implemented method also includes identifying a bitmap associated with the buffer, the bitmap being in a local memory of the first processing unit. The computer-implemented method also includes updating a bit from the bitmap to indicate that the buffer has been freed, the bit corresponding to the buffer.

Deallocation of memory buffer in multiprocessor systems

In a logically partitioned host computer system comprising host processors (host CPUs) partitioned into a plurality of guest processors (guest CPUs) of a guest configuration, a perform topology function instruction is executed by a guest processor specifying a topology change of the guest configuration. The topology change preferably changes the polarization of guest CPUs, the polarization being related to the amount of a host CPU resource provided to a guest CPU.

Execution of an instruction for performing a configuration virtual topology change

Testing for pending external interruptions. A Test Pending External Interruption instruction tests for pending external interruptions. The test for pending external interruptions is based on one or more program-specified subclasses, regardless of whether the machine is enabled for those classes of interruption. The instruction provides an indication for those subclasses being tested of whether there are any pending external interruptions for those subclasses.

Test pending external interruption instruction

Aspects of the present invention include a method, system and computer program product that implements a memory management scheme for each processor in a multiprocessor system. The method includes pre-allocating, for each processor in a multiprocessor system, a set of memory buffers; and implementing a metadata bitmap for each pre-allocated set of memory buffers, wherein the metadata bitmap for each pre-allocated set of memory buffers comprises a plurality of bits, and wherein each of the plurality of bits is indicative of a usage state of a corresponding one of the memory buffers within each pre-allocated set of memory buffers.

Pre-allocating memory buffers by physical processor and using a bitmap metadata in a control program

Examples of techniques for pre-allocating save areas of memory of a computer processing system are disclosed. In one example implementation according to aspects of the present disclosure, a computer-implemented method may include initiating, by a host processing device, a control program. The method may further include, responsive to initiating the control program, pre-allocating, by the host processing device, a plurality of save areas for each of a plurality of processors, wherein the plurality of save areas are anchored in a fixed area of the memory for each of the plurality of processors.

Pre-allocating save areas of a memory

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Poughquag, NY, United States of America

Jeffrey Paul Kubala