Analog Devices,inc.

Jeffrey Paul Bray

Carroll Clifton Speir

Eric Otte

Stephen Robert Kosic

Nevena Rakuljic

Corey Petersen

To address non-linearity, an on-chip linearization scheme is implemented along with an analog-to-digital converter (ADC) to measure and correct/tune for non-linearities and/or other non-idealities of the signal path having the ADC. The on-chip linearization scheme involves generating one or more test signals using an on-chip digital-to-analog converter (DAC) and providing the one or more test signals as input to the signal path to be linearized, and estimating non-linearity based on the one or more test signals and the output of the ADC. Test signals can include single-tone signals, multi-tone signals, and wideband signals spread over a range of frequencies. A time-delayed interleaving clocking scheme can be used to achieve a higher data rate for coefficient estimation without having to increase the sample rate of the ADC.

Signal path linearization

Analog-to-digital converters (ADCs) can have errors which can affect their performance. To improve the performance, many techniques have been used to compensate or correct for the errors. When the ADCs are being implemented with sub-micron technology, ADCs can be readily and easily equipped with an on-chip microprocessor for performing a variety of digital functions. The on-chip microprocessor and any suitable digital circuitry can implement functions for reducing those errors, enabling certain undesirable artifacts to be reduced, and providing a flexible platform for a highly configurable ADC. The on-chip microprocessor is particularly useful for a randomized time-interleaved ADC. Moreover, a randomly sampling ADC can be added in parallel to a main ADC for calibration purposes. Furthermore, the overall system can include an efficient implementation for correcting errors in an ADC.

Microprocessor-assisted calibration for analog-to-digital converter

Efficient calibration of errors in multi-stage analog-to-digital converter

A method and a device for canceling an offset voltage in an output of a comparator circuit include applying a signal to a first input of the comparator as a function of an initial tap point in a resistor ladder. While the signal is applied to the first input, a nominal voltage is applied to a second input of the comparator, and then an output of the comparator is analyzed. The signal to the first input is changed in response to the analyzing, by accessing a different tap point in the resistor ladder.

Foreground techniques for comparator calibration

A method and a corresponding device for performing a background calibration of a comparator in a circuit having a plurality of stages that are connected in a pipelined fashion to an input signal. A digital value of a residue signal, which is output from a first stage in the plurality of stages to a subsequent stage in the plurality of stages, is calculated. The value of the residue signal is compared to at least one threshold. Based on the comparison, a triggering threshold of a selected comparator in the first stage may be adjusted.

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San Diego, CA, United States of America

Jeffrey Paul Bray