Micron Technology Incorporated

Round Rock Research, LLC

Nan Ya Technology Corporation

Hughes Aircraft Company

Jeffrey P Wright

Hua Zheng

Timothy B Cowles

Victor Wong

Timothy Mowry Hollis

Dean D Gans

Robert Nasry Hasbun

Alan John Wilson

James S Cullum

Michael Amiel Shore

William F Jones

Mirmajid Seyyedy

Todd D Farrell

Steven F Schicht

Brent Keeth

Todd A Merritt

Kevin G Duesman

Donald M Morgan

Yantao Ma

Patrick J Mullarkey

Christopher K Morzano

Jeffery W Janzen

James E Davis

Paul M Fuller

Warren L Boyer

John David Porter

Jongtae Kwak

Hal W Butler

Jeff W Janzen

Mehul Nagrani

Scott James Derner

Charles L Ingalls

Dong Pan

Adrian E Ong

Kurt D Beigel

Manny K Ma

Jaime Cummins

Kevin J Ryan

Huy Thanh Vo

Douglas John Cutter

Fan Ho

Kenneth Marion Curewitz

Brett M Debenham

Kim M Pierce

Shizhong Mei

J Wayne Thompson

Bryce D Cook

Dien S Luong

Jim Cullum

Glen Earl Hush

Aaron Preston Boehm

Kang-Yong Kim

Eugene H Cloud

Sujeet V Ayyapureddi

Kang Yong Kim

Simon J Lovett

Eric J Stave

Suryanarayana B Tatapudi

Bryan David Kerstetter

Mark K Hadrick

Charles A Finnila

Judith L Hvizdak

A memory controller and a physical interface layer may accommodate multiple memory types. In some examples, the memory controller and/or PHY may include a register that includes operating parameters for multiple operating modes. Different operating modes may be compatible with different memory types. In some examples, the memory controller and physical interface may be included in a system for testing multiple memory types. The system may provide multiple interfaces for communicating with the memory. The different communication types may be used for performing different tests and/or simulating different types of devices that may utilize the memory.

Multi-modal memory apparatuses and systems

Methods, systems, and devices for communicating data with stacked memory dies are described. A first semiconductor die may communicate with an external computing device using a binary-symbol signal including two signal levels representing one bit of data. Semiconductor dies may be stacked on one another and include internal interconnects (e.g., through-silicon vias) to relay an internal signal generated based on the binary-symbol signal. The internal signal may be a multi-symbol signal modulated using a modulation scheme that includes three or more levels to represent more than one bit of data. The multi-level symbol signal may simplify the internal interconnects. A second semiconductor die may be configured to receive and re-transmit the multi-level symbol signal to semiconductor dies positioned above the second semiconductor die.

Communicating data with stacked memory dies

Systems, methods and apparatuses to log memory errors in memory devices that can perform wear leveling based on physical addresses used in the memory devices to address select memory cells. For example, a controller of a memory sub-system communicates with a memory device installed in the memory sub-system to access memory cells in the memory device. During the communication to access memory cells in the memory device, the controller can determine a memory error at a first address. If the controller transmits the first address to the memory device for memory access at the time of the memory error, the memory device converts the first address to a second address to perform the memory access. The controller can be configured to determine the second address and record, in an error log, the memory error in association with the second address.

Error logging for a memory device with on-die wear leveling

Methods, systems, and devices that support variable modulation schemes for memory are described. A device may switch between different modulation schemes for communication based on one or more operating parameters associated with the device or a component of the device. The modulation schemes may involve amplitude modulation in which different levels of a signal represent different data values. For instance, the device may use a first modulation scheme that represents data using two levels and a second modulation scheme that represents data using four levels. In one example, the device may switch from the first modulation scheme to the second modulation scheme when bandwidth demand is high, and the device may switch from the second modulation scheme to the first modulation scheme when power conservation is in demand. The device may also, based on the operating parameter, change the frequency of the signal pulses communicated using the modulation schemes.

Variable modulation scheme for memory device access or operation

Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

Multiple concurrent modulation schemes in a memory system

Methods, systems, and devices for multiplexing distinct signals on a single pin of a memory device are described. Techniques are described herein to multiplex data using a modulation scheme having at least three levels. The modulated data may be communicated to multiple memory dies over a shared bus. Each of the dies may include a same or different type of memory cell and, in some examples, a multi-level signaling scheme may be pulse amplitude modulation (PAM). Each unique symbol of the modulated signal may be configured to represent a plurality of bits of data.

Multiplexing distinct signals on a single pin of a memory device

A semiconductor device assembly includes a substrate and a die coupled to the substrate. The die includes a first contact pad electrically coupled to a first circuit on the die including at least one active circuit element and a second contact pad electrically coupled to a second circuit on the die including only passive circuit elements. The substrate includes a substrate contact electrically coupled to the first contact pad, and the substrate is electrically isolated from the second contact pad.

Semiconductor devices with package-level configurability

Apparatuses and methods for targeted row refreshes are disclosed herein. In an example apparatus, a predecoder receives a target row address and determines whether a target row of memory associated with the target row address is a primary or a redundant row of memory. The predecoder is further configured to cause one or more rows of memory physically adjacent the primary row of memory to be refreshed if the primary row is the target row or one or more rows of memory physically adjacent the redundant row of memory to be refreshed if the redundant row of memory is the target row of memory.

Apparatuses and methods for targeted refreshing of memory

Methods, systems, and devices that supports dual-mode modulation in the context of memory access are described. A system may include a memory array coupled with a buffer, and a multiplexer may be coupled with the buffer, where the multiplexer may be configured to output a bit pair representative of data stored within the memory array. The multiplexer may also be coupled with a driver, where the driver may be configured to generate a symbol representative of the bit pair that is output by the multiplexer.

Memory system that supports dual-mode modulation

Growing community of inventors

Boise, ID, United States of America

Jeffrey P Wright