International Business Machines Corporation

Globalfoundries Inc.

Semiconductor Components Industries, LLC

Other

Siemens Aktiengesellschaft

Cornell Research Foundation Inc.

Infineon Technologies Ag

Ultratech, Inc.

Infineon Technologies LLC

Globalfoundries U.S. 2 LLC

Elpis Technologies Inc.

Jeffrey P Gambino

Anthony K Stamper

Wolfgang Sauter

Christopher David Muzzy

Timothy Harrison Daubenspeck

Mark David Jaffe

James William Adkisson

John J Ellis-Monaghan

Timothy Dooling Sullivan

Jack Allan Mandelman

Zhong-Xiang He

Robert K Leidy

Kirk David Peterson

Timothy Joseph Dalton

Jed Hickory Rankin

Stephen Ellinwood Luce

Edward Crandal Cooney, Iii

Gary Bela Bronner

Carl John Radens

Steven M Shank

Fen Chen

Charles Leon Arvin

Ramachandra Divakaruni

Edmund Juris Sprogis

John Anthony Fitzsimmons

William R Tonti

Kerry Bernstein

Tom C Lee

Daniel C Edelstein

Steven H Voldman

Douglas Duane Coolbaugh

Louis L Hsu

Andrew Herbert Simon

David L Questad

Kevin Shawn Petrarca

Andres Bryant

Son Van Nguyen

Baozhen Li

Elbert Emin Huang

Robert Mark Rassel

Richard Anthony Conti

Brent A Anderson

Qizhi Liu

Sampath Purushothaman

Matthew Earl Colburn

Thomas M Shaw

Satyanarayana Venkata Nitta

Vincent James McGahay

Claude Louis Bertin

Cyril Cabral, Jr

Robert Russell Robison

Alvin Jose Joseph

Michael Patrick Chudzik

Herbert Lei Ho

Chandrasekhar Narayan

Lawrence Alfred Clevenger

Mukta G Farooq

Kenneth Parker Rodbell

Bucknell Chapman Webb

Ronald G Filippi

Richard Paul Volant

Xiao Hu Liu

Hyun K Lee

Rajarao Jammy

Edward J Nowak

Sebastian Theodore Ventrone

Evan G Colgan

Takeshi Nogami

Jeffrey Bowman Johnson

Laertis Economikos

Renee Tong Mo

Eric Andrew Joseph

Xuefeng Liu

David Louis Harame

Alain F Loiseau

David John Russell

Solomon Assefa

John Maxwell Cohn

Randy William Mann

Raschid Jose Bezama

James Stuart Dunn

Theodorus E Standaert

Toshiharu Furukawa

Katsuya Okumura

Ping-Chuan Wang

Geng Wang

Haizhou Yin

Toshiaki Kirihata

Dominic Joseph Schepis

Leland Chang

Xin Ru Wang

Jack Oon Chu

Qinghuang Lin

Paul Stephen Andry

Hanyi Ding

Eduard Albert Cartier

Griselda Bonilla

Wilbur David Pricer

Swarnal Borthakur

Wagdi William Abadeer

An imaging device may include single-photon avalanche diodes (SPADs). To mitigate crosstalk, isolation structures may be formed around each SPAD. The isolation structures may include front side deep trench isolation structures that extend partially or fully through a semiconductor substrate for the SPADs. The isolation structures may include a metal filler such as tungsten that absorbs photons. The isolation structures may include a p-type doped semiconductor liner to mitigate dark current. The isolation structures may include a buffer layer such as silicon dioxide that is interposed between the metal filler and the p-type doped semiconductor liner. The isolation structures may have a tapered portion or may be formed in two steps such that the isolation structures have different portions with different properties. An additional filler such as polysilicon or borophosphosilicate glass may be included in some of the isolation structures in addition to the metal filler.

Semiconductor devices with single-photon avalanche diodes and isolation structures

Implementations of semiconductor packages may include: a digital signal processor having a first side and a second side and an image sensor array, having a first side and a second side. The first side of the image sensor array may be coupled to the second side of the digital signal processor through a plurality of hybrid bond interconnect (HBI) bond pads and an edge seal. One or more openings may extend from the second side of the image sensor array into the second side of the digital signal processor to an etch stop layer in the second side of the digital signal processor. The one or more openings may form a second edge seal between the plurality of HBI bond pads and the edge of the digital signal processor.

Edge seals for semiconductor packages

A method includes etching a through-substrate via (TSV) in a substrate from a backside of the substrate. The substrate has a device layer on a frontside. The method further includes depositing a conformal spacer layer on the backside of the substrate, and sidewalls and a bottom of the TSV, and etching the spacer layer to form a self-aligned mask for etching a contact opening at the bottom of TSV to a metal pad in the device layer, and etching the contact opening at the bottom of TSV to the metal pad in the device layer. The method further includes disposing a conductive material layer in the TSV and the contact opening to make a vertical interconnection from the backside of the substrate to the metal pad in the device layer.

Self-aligned contact openings for backside through substrate vias

Implementations of image sensor devices may include a through-silicon-via (TSV) formed in a backside of an image sensor device and extending through a material of a die to a metal landing pad. The metal landing pad may be within a contact layer. The devices may include a TSV edge seal ring surrounding a portion of the TSV in the contact layer and extending from a first surface of the contact layer into the contact layer to a depth coextensive with a depth of the TSV.

Backside illumination image sensors

A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in a disorderly arrangement on a substrate. The metal silicide nanowire network can be formed by applying a solution that contains silicon nanowires onto the substrate, forming a metal layer on the silicon nanowires, and performing a silicidation anneal such that the metal silicide nanowires are fused together in a disorderly arrangement, forming a mesh. After the silicidation anneal is performed, any unreacted silicon or metal can be selectively removed.

Method of forming a metal silicide transparent conductive electrode

Implementations of methods of forming capacitors may include depositing a first metal layer over a substrate, forming a photoresist layer over the first metal layer, patterning the photoresist layer, patterning the first metal layer using the pattern of the photoresist layer, depositing a dielectric layer over the first metal layer, and depositing a second metal layer over the dielectric layer to form a metal-insulator-metal capacitor.

Methods of forming capacitors

A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.

Stacked transistor assembly with dual middle mounting clips

A method of forming a metal silicide nanowire network that includes multiple metal silicide nanowires fused together in an orderly arrangement on a substrate. The metal silicide nanowire network can be formed by printing a first set of multiple parallel silicon nanowires on the substrate and printing a second set of multiple parallel silicon nanowires over the first set of multiple parallel silicon nanowires such that said first set is perpendicular to said second set. A metal layer can be formed on the silicon nanowires. A silicidation anneal process is performed such that metal silicide nanowires are formed and fused together in an orderly arrangement, forming a grid network. After the silicidation anneal is performed, any unreacted silicon or metal can be selectively removed.

A dual bond pad structure for a wafer with laser die attachment and methods of manufacture are disclosed. The method includes forming a bonding layer on a surface of a substrate. The method further includes forming solder bumps on the bonding layer. The method further includes patterning the bonding layer to form bonding pads some of which comprise the solder bumps thereon. The method further includes attaching a laser diode to selected bonding pads using solder connections formed on the laser diode. The method further includes attaching an interposer substrate to the solder bumps formed on the bonding pads.

Dual bond pad structure for photonics

Implementations of semiconductor packages may include a first die including a plurality of contact pads, a second die including a plurality of contact pads, a plurality of solder interconnects bonding the plurality of contact pads of the first die to the plurality of contact pads of the second die, and a plurality of magnetic particles each coated in an oxide included in each of the plurality of solder interconnects.

Semiconductor package having magnetic interconnects and related methods

Photodiode structures and methods of manufacture are disclosed. The method includes forming a waveguide structure in a dielectric layer. The method further includes forming a Ge material in proximity to the waveguide structure in a back end of the line (BEOL) metal layer. The method further includes crystallizing the Ge material into a crystalline Ge structure by a low temperature annealing process with a metal layer in contact with the Ge material.

Photodiode structures

Moisture detection and ingression monitoring systems and methods of manufacture are provided. The moisture detection structure includes chip edge sealing structures including at least one electrode forming a capacitor structured to detect moisture ingress within an integrated circuit. The at least one electrode and a second electrode of the capacitor is biased to ground and to a moisture detection circuit or vice versa, respectively.

Moisture detection and ingression monitoring systems and methods of manufacture

Growing community of inventors

Westford, VT, United States of America

Jeffrey P Gambino