Altera Corporation

Altera Corporaton

Jeffrey Orion Pritchard

Tim Allen

Michael Fairman

Timothy Allen

Bryan H Hoyer

David James Lau

James M Brown

Mike Fairman

Philippe Molson

Kerry S Veenstra

James Loran Ball

Aaron Ferrucci

Todd Wayne

Jesse Kempa

Jarrod Colin James Blackburn

Paul Norbert Scheidt

Chris Adler

Scott Raymond Frazier

Kevin Pykkonen

Karl Ginter

Paul Metzgen

David Arthur Van Brink

Nathan Glenn Knight

David Van Brink

Joel A Seely

Eric Joseph Lechner

Richard Noble Hill

Peter Hutkins

Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences such as high-level language software critical loops are converted into read/transform/write (RXW) processes with buffer based flow control between the processes. Having separate read and write processes allows an arbitrary number of sequential reads/writes to occur in any order, subject to buffer size, allowing bursting/sequential transactions that are more efficient than random accesses.

High-level language code sequence optimization for implementing programmable chip designs

A system for designing a circuit, which includes a module, uses a computer. A user may program or adapt the computer to perform computer-aided design functions. The computer obtains a description of the module from the user. The computer parses the description of the module to identify a port of the module, and to obtain information about the port. The computer presents to the user the information that it has obtained about the port.

Apparatus and methods for importing hardware design and generating circuit interfaces

Methods and apparatus are provided for allowing interconnection between ports associated with primary and secondary components in an embedded system. Ports may only support a particular bus type or set of attributes and a variety of ports may be incompatible. Bus types include Peripheral Components Interface (PCI) and Advanced Microcontroller Bus Architecture (AMBA) while attributes include bursting, non-bursting, word-wide, byte-wide, etc. Port adapters components are automatically selected from a library of port adapter components to allow connection of incompatible ports. Port adapters can be shared, chained, and intelligently selected for increased efficiency.

Tool selection and implementation of port adapters

Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences or subroutines provided in a high-level language are overloaded with information to specify the number of hardware resources such as logic elements or functional blocks used to implement the code on a programmable chip. Code sequences remain compliant with standard high-level language compilers while also being able to provide resource count information to high-level language to hardware compilers.

Allocating hardware resources for high-level language code sequences

Various high-level languages are used to specify hardware designs on programmable chips. The high-level language programs include pointer operations that may have same iteration and future iteration dependencies. Single loop iteration pointer dependencies are considered when memory accesses are assigned to clock cycles. Multiple loop iteration pointer dependencies are considered when determining how often new data can be entered into the generated hardware pipeline without causing memory corruption. A buffer can be used to forward data from a memory write to a future read.

Scheduling optimization of aliased pointers for implementation on programmable chips

Methods and apparatus are provided for allowing efficient clock domain crossing management in programmable chip systems. Components associated with different clock domains can be analyzed. Clock domain crossing components are automatically selected from a library of clock domain crossing components to allow connection between disparate clock domains. Clock domain crossing components can be shared, chained, and intelligently selected for increased efficiency.

Selection of port adapters for clock crossing boundaries

Methods and apparatus are provided for allowing a master component such as a processor on a programmable chip to access memory using unaligned addresses. An adapter connected to a master component determines if a master component memory access request is aligned. If the access request is aligned, the request is forwarded to memory and a response is provided to the master component. If the access request is unaligned, the adapter sends multiple access requests to memory and processes the responses in order to provide a correct response to the master component.

Adapter allowing unaligned access to memory

Techniques and mechanisms provide numerous representations and/or control of component interconnections in a digital design. For example, aspects of the invention provide a connection panel where connections can be presented in different modes. The different modes can run concurrently with each other or separately from each other. The different modes can also be manually or automatically selected to switch from one mode to another mode. For instance, the modes can be manually selected using an on-screen button or automatically selected by examining the location of the mouse pointer on the connection panel. Based on the different modes, component interconnections can be easily and efficiently handled and presented. Further, components can be automatically organized to minimize the number of crossing interconnects between them and/or maximize the amount of interconnection information presented.

Tool with graphical interconnect matrix

Methods and apparatus are provided for implementing parameterizable processor cores and peripherals on a programmable chip. An input interface such as a wizard allows selection and parameterization of processor cores, peripherals, as well as other modules. The logic description for implementing the modules on a programmable chip can be dynamically generated, allowing extensive parameterization of various modules. Dynamic generation also allows the delivery of device driver logic onto a programmable chip. The logic description can include information for configuring a dynamically generated bus module to allow connectivity between the modules as well as connectivity with other on-chip and off-chip components. The logic description, possibly comprising HDL files, can then be automatically synthesized and provided to tools for downloading the logic description onto a programmable chip.

Methods and apparatus for implementing parameterizable processors and peripherals

Methods and apparatus are provided for providing a first master component with access to a first slave component while a second master component is accessing a second slave component in a system. The system may include a processor core and peripherals implemented on an integrated circuit. A slave side arbitrator corresponding to a single slave component and coupled to multiple master components can be used to provide a master component access to a slave component.

Master and slave side arbitrators associated with programmable chip system components

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Santa Cruz, CA, United States of America

Jeffrey Orion Pritchard