Seagate Technology Incorporated

Micron Technology Incorporated

Other

Lsi Corporation

Jeffrey Munsil

Jackson L Ellis

Mark Ish

Timothy Lawrence Canepa

Michael B Danielson

Ryan James Goss

Steven Scott Williams

Stephen D Hanna

Carl E Forhan

Scheheresade Virani

Jeffrey L Williams

James Ruane

Methods, systems, and devices for detecting information modification in a memory system are described. A system may generate a first value, such as a first hash value, from information stored in storage component. The system may then generate a second value, such as a second hash value, from content stored in the storage component. After generating the second value, the system may compare the second value to the first value. The system may then determine the modification status of the information based on the comparison, and implement one or more operations based on the modification status.

Detecting information modification in a memory system

Implementations described herein relate to memory device log data storage. In some implementations, a memory device may store a first data stream associated with a first type of log data in a circular buffer. The memory device may store a second data stream associated with a second type of log data in another memory location. The memory device may detect an event included in the second data stream that is associated with an attribute level that satisfies a threshold. The memory device may write data stored in the circular buffer after a time at which the event is detected to a non-volatile memory based on the attribute level satisfying the threshold, wherein the data stored in the circular buffer is stored in the non-volatile memory in connection with data associated with the event.

Memory device log data storage

A processing device of a memory sub-system is configured to receive, from a host system, host data to be stored at a memory sub-system in an encrypted form; determine that the host data exceeds a threshold size associated with an encryption operation; separate the host data into a plurality of segments based on the threshold size associated with the encryption operation; determine that a particular segment of the plurality of segments does not satisfy a size requirement of data associated with the encryption operation; modify the particular segment to satisfy the size requirement of data associated with the encryption operation; encrypt each of the plurality of segments based on the encryption operation; and store the encrypted plurality of segments at the memory sub-system.

Modification of a segment of data based on an encryption operation

Host data can be received at a memory sub-system. A determination can be made that the host data exceeds a threshold size associated with an encryption operation. The host data can be separated into segments based on the threshold size associated with the encryption operation. Each of the segments can be encrypted based on the encryption operation. Furthermore, the encrypted segments can be stored at the memory sub-system.

A method includes compressing input data to form compressed data and comparing a size of the compressed data to a maximum allowed size determined from a fixed sector size for a lower tier of the multi-tier storage system and a minimum pad length for a pad that is stored in the same sector as the compressed data when the compressed data is migrated to the lower tier. When the size of the compressed data is greater than the maximum allowed size, the input data is stored instead of the compressed data in an upper tier of the multi-tier storage system.

Fixed record media conversion with data compression and encryption

Method and apparatus for managing data in a memory, such as a flash memory. A memory module has a non-volatile memory (NVM) and a memory module electronics (MME) circuit configured to program data to and read data from solid-state non-volatile memory cells of the NVM. A map structure associates logical addresses of user data blocks with physical addresses in the NVM at which the user data blocks are stored. A controller circuit arranges the user data blocks into map units (MUs), and directs the MME circuit to write the MUs to a selected page of the NVM. The controller circuit updates the map structure to list only a single occurrence of a physical address for all of the MUs written to the selected page. The map structure is further updated to list an MU offset and an MU length for each of the MUs written to the selected page.

Low overhead mapping for highly sequential data

Apparatus and method for managing namespaces in a Non-Volatile Memory Express (NVMe) controller environment. A non-volatile memory (NVM) is arranged to store map units (MUs) as addressable data blocks in one or more namespaces. A forward map has a sequence of map unit address (MUA) entries that correlate each of the MUs with the physical locations in the NVM. The MUA entries are grouped into immediately adjacent, contiguous ranges for each of the namespaces. A base MUA array identifies the address, within the forward map, of the beginning MUA entry for each namespace. A new namespace may be added by appending a new range of the MUA entries to the forward map immediate following the last MUA entry, and by adding a new entry to the base MUA array to identify the address, within the forward map, of the beginning MUA entry for the new namespace.

Managing multiple namespaces in a non-volatile memory (NVM)

A data storage device with one or more buffers can employ buffer tenure management with at least a data storage device having a first buffer, a second buffer, a buffer manager, and a non-volatile memory. The first buffer can be located on-chip while the second buffer is located off-chip. The first buffer may be filled with data having a tenure of less than a predetermined tenure threshold as directed by the buffer manager.

Data storage device with buffer tenure management

Apparatus and method for managing map data in a data storage device. A programmable processor issues a find command to locate and place a requested map page of a map structure into a first cache to service a received host command. A non-programmable hardware circuit searches a forward table to determine whether the requested map page is in a second cache, and if so, loads the map page to the first cache. If not, the hardware circuit requests the requested map page from a back end processor which retrieves the requested map page from a non-volatile memory (NVM), such as a flash memory array. The hardware circuit searches a reverse table and the first cache to select a candidate location in the second cache for the retrieved requested map page from the NVM, and directs the storage of a copy of the requested map page at the candidate location.

Hardware based map acceleration using forward and reverse cache tables

Described embodiments provide for authenticating a user request for access to at least a portion of an encrypted storage device. First, the request for access to at least a portion of the encrypted storage device is received. The request includes a plaintext password. A hash module generates a hashed version of the received plaintext password based on an authentication hash key. A hashed value of the generated plaintext password is retrieved from a key storage. A hash comparator compares the hashed version of the received plaintext password with the retrieved hashed value of the generated plaintext password. If the hashed version of the received plaintext password and the retrieved hashed value of the generated plaintext password are equal, the user is authenticated for access to at least a portion of the encrypted storage device. Otherwise, the user is denied access to the encrypted storage device.

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Fort Collins, CO, United States of America

Jeffrey Munsil