Atmel Corporation

Micron Technology Incorporated

Jeffrey Ming-Hung Tsai

Johnny Chan

Tin-Wai Wong

Yingda Dong

Ching-Huang Lu

Dheeraj Srinivasan

Philip S Ng

Erwin E Yu

Jinshu Son

Luyen Tien Vu

Tsung-Ching Wu

Alan L Renninger

Lakshmi Kalpana Vakati

Vinh Q Diep

Ekamdeep Singh

Lu Tong

Ashish Ghai

Chai Chuan Yao

Sheng Huang Lee

Matthew Ivan Warren

A memory device comprising a memory array and control logic operatively coupled with the memory array. The control logic is to: detect a program operation directed at a selected wordline of multiple wordlines of the memory array; determine, during an initial phase of the program operation, whether a program voltage being applied to the selected wordline satisfies a threshold program voltage; add, in response to the program voltage not satisfying the threshold program voltage, a base offset voltage to an initial pass voltage to generate a higher pass voltage, the initial pass voltage being a percentage of an initial program voltage; and cause the higher pass voltage to be applied to a remainder of the multiple wordlines other than the selected wordline.

Selective increase and decrease to pass voltages for programming a memory device

Control logic in a memory device executes a programming operation to program the set of memory blocks of the set of memory planes to a set of a programming levels. In response to determining at least a portion of a first memory block passed a program verify operation associated with a last programming level of the set of programming levels, the control logic executes a first program sub-operation to terminate the programming operation with respect to a first subset of one or more memory planes of the set of memory planes that passed the program verify operation associated with the last programming level and identify a second subset of one or more memory planes that failed the program verify operation associated with the last programming level. The control logic executes a second program sub-operation to apply a trim set to the second subset of one or more memory planes that failed the program verify operation of the last programming level.

Multiple plane programming with quick plane programming termination and lagging plane boosting

A device includes a memory array and a sense circuit coupled with the memory array. The sense circuit includes a sense node coupled with a data line of the memory array. A first sensing path includes a first transistor having a first gate coupled with the sense node. A second sensing path includes a second transistor having a second gate coupled with the sense node. A first threshold voltage of the first transistors differs from a second threshold voltage of the second transistor by a threshold voltage gap.

Sense circuit to sense two states of a memory cell

Some embodiments include a device having storage node and a latch circuit coupled to the storage node to latch data provided to the storage node during one of a first mode and a second mode of the device. The latch circuit includes a first transistor, a second transistor, and a third transistor coupled between a first voltage node and a second voltage node. The third transistor is configured to selectively turn on and off in the first and second modes. Other embodiments are described.

Apparatus and methods for a high-voltage latch

A programming circuit and method to apply a controlled or predetermined voltage pulse for charge transfer to or from the floating gate of a non-volatile memory cell in an incremental manner to control the overall voltage across the gate oxide. Voltage above a transfer threshold voltage, such as above a tunneling threshold voltage, is applied in a stepwise charge transfer manner to or from the floating gate up to a voltage limit that is below the thin oxide damage threshold. Controlling the overall voltage avoids oxide breakdown and enhances reliability.

Circuit to control voltage ramp rate

An improved CMOS high-voltage latch that stores data bits to be written to memory cells of a non-volatile memory is connected to a Vdd supply voltage during a standby mode of operation and during a load-data mode of operation. During a high-voltage write mode of operation, the HV terminal is connected to a HIGH-VOLTAGE supply voltage. A cross-coupled high-voltage CMOS latch is connected between the HV terminal and a ground terminal and has a latch input node B and a latch output node A. An input buffer is connected between the HV terminal and the ground terminal and has an input terminal connected to a DATA INPUT terminal. An output terminal of the input buffer is connected to the latch input node B. The input buffer is enabled during a load-data mode of operation to load data from a DATA INPUT terminal to the latch input node B of the cross-coupled high-voltage CMOS latch.

Apparatus for eliminating leakage current of a low Vt device in a column latch

A power down reset circuit for asserting a signal when a first Vvoltage falls below a voltage threshold. The circuit has at least one diode coupled to the first Vvoltage. The at least one diode is configured to produce a second voltage. At least one capacitor is coupled to the at least one diode to maintain the second voltage. A voltage detector asserts a signal when the first Vvoltage drops below a threshold level. The voltage detector is powered by the second voltage and is coupled to the at least one diode.

Power down detection circuit

A flash memory programming process incorporates two charge pumps per byte of bit cells. Placing a data 'one' value in each bit cell erases an entire memory device. Before programming each cell, a prospective data content is scrutinized. If a data 'zero' is to be applied to the bit cell, a charge pump engages to bias the cell and activate a hot electron injection process to affect the programming. If a data &#x201c;one&#x201d; is to be applied to the bit cell, no programming activity is undertaken and the process increments to the next bit cell in the data structure. Therefore, total programming time is reduced proportionally to the number of data &#x201c;one&#x201d; bits to be programmed. Where more than one charge pump is engaged in parallel to a data structure, total programming time is further reduced when two data &#x201c;one&#x201d; values are to be programmed in parallel.

Growing community of inventors

San Jose, CA, United States of America

Jeffrey Ming-Hung Tsai