National Semiconductor Corporation

Jeffrey Mark Huard

David Lindsay Broughton

Kim Yeow Wong

Wayne Porter

A phase-frequency detector (PFD) having substantially linear phase error gain within a predetermined phase error range centered about zero phase error when used in a delta sigma phase-locked loop (PLL). The output signals (e.g., charge pump control signals), which are also used to reset the input circuitry, are fed back with asymmetrical signal delays, thereby causing one of the output signals to remain in an asserted state for a substantially constant time duration at least during when a difference between the reference and feedback signal phases is within a predetermined phase difference range centered about zero phase difference.

Phase-frequency detector with linear phase error gain near and during phase-lock in delta sigma phase-locked loop

A circuit for controlling a phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock includes frequency dividers with selectable divisors for the reference and feedback signals, and a phase detector having a charge pump output circuit with selectable output current ranges. During acquisition of phase lock by the PLL, the divisors for the reference and feedback signal frequency dividers are increased by the same factor, and the charge pump current range is increased by the same ratio. As a result, the reference rate is decreased as the charge pump current range is increased simultaneously by the same ratio. Meanwhile, the linear loop bandwidth and phase margin remain substantially constant.

Control circuit for phase-locked loop (PLL) with reduced cycle slip during acquisition of phase lock

Oscillator control circuitry for a phase lock loop, including phase detection circuitry, control signal generator circuitry, bias control circuitry and charge pump circuitry. The control signal generator circuitry introduces specific and distinct time delays to the phase signals from the phase detection circuitry representing the phase difference between the reference and oscillator output signals. These time delays cause the bias control circuitry to enable and disable the output charge pump circuitry slightly before and after, respectively, those time intervals during which an output source (&ldquo;pump up&rdquo;) or sink (&ldquo;pump down&rdquo;) current is needed to drive the oscillator via the loop filter. This produces charge pump circuitry output signals with significantly faster rise and fall times and shorter pulse widths, thereby resulting in a charge pump output signal with higher SNR and reduced spurious signal energy.

Oscillator control circuitry for phase lock loop providing enhanced phase noise and spurious signal performance

A high-speed differential-feedback cascode sense amplifier includes an output stage and a voltage clamp. The voltage clamp is coupled to a pair of bit-sense lines of a memory system or other sense line source. The output stage is coupled to the output of the voltage clamp for generating an output signal having a logic state determined according to the current difference across the bit-sense lines. The voltage clamp includes a pair of transistors (e.g., cascode transistors) in cascode to a differential-feedback gain stage. Bit-sense lines are coupled to the cascode transistors and the differential-feedback gain stage. The gain stage amplifies the current difference across the bit-sense lines to define feedback voltage signals input to the cascode transistors. The parasitic voltage difference across the bit-sense lines resulting from driving the cascode transistors is small, approximately 3-7 mV for an ECL sense amplifier. Because the bit-sense lines are capacitively loaded very heavily, the small parasitic voltage difference across the bit-sense lines enables faster charging/discharging of the bit-sense lines for a memory access. The current difference acros the bit-sense lines is amplified by the gain stage to define feedback voltage signals having a relative voltage difference of approximately 45 milli-Volts. The output of the cascode transistors have a relative voltage difference of approximately 200-400 mV. The output stage further increases the voltage difference to produce two signals, one at each ECL logic state. One of the signal paths forms the sense amplifier output. The addressed memory contents determine whether the signal path for the output is at the logic high level or the logic low voltage level.

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Puyallup, WA, United States of America

Jeffrey Mark Huard