Stretch, Inc.

Xilinx, Inc.

Jeffrey Mark Arnold

Scott David Johnson

Albert RenRui Wang

Gareld Howard Banta

Charle' R Rupp

Nabeel Shirazi

Joseph H Hassoun

Rafael Czernek Camarota

Anindita Patra

Stephen L Bade

Srinivas Beeravolu

Chukwuweta Chukwudebe

Charle′ R Rupp

Timothy L Garverick

Disclosed approaches for creating a circuit design involving a network-on-chip (NoC) include instantiating in a memory of a computer system logic blocks and logical NoC (LNoC) blocks. Each logic block specifies a function of the circuit design and is communicatively coupled to another logic block through an LNoC block. The LNoC blocks are aggregated into a traffic specification that specifies connections between ingress circuits and egress circuits of the NoC. The traffic specification is compiled into configuration parameters for circuits of the NoC, and the logic blocks are compiled into implementation data for the target IC by the computer processor. The target IC can then be configured with the configuration parameters and implementation data.

Preparation of circuit designs for system-on-chip devices and implementation of circuitry using instances of a logical network-on-chip

A processing system with reconfigurable instruction extensions includes a processor, programmable logic, a register file, and a load/store module. The processor executes a computer program comprising a set of computational instructions and at least one instruction extension. The programmable logic receives configuration information to configure the programmable logic for the instruction extension and executes the instruction extension. The register file is coupled to the programmable logic and stores data. The load/store module transfers the data directly between the register file and a system memory.

Programmable logic configuration for instruction extensions

A system, apparatus and a method for implementing multifunctional memories is disclosed. The multifunctional memories perform a variety of functions during execution of extended instructions in a reconfigurable data path processor composed of processing nodes. In one embodiment, a processing node can be comprised of modular processing elements to perform computations associated with an extended instruction. Also, such a node includes at least two multifunctional memories and a data flow director configured to selectably couple the first multifunctional memory and the second multifunctional memory. The data flow director is configured to route data out from a first multifunctional memory of the two multifunctional memories while data is being routed into a second multifunctional memory. In another embodiment, a processing node is configured to compute a function output based on a number of Boolean functions, wherein at least one of the multifunctional memories is configured as a look-up table ('LUT').

System, apparatus and method for implementing multifunctional memory in reconfigurable data path processing

A video processing system with reconfigurable instructions includes a processor, a first register file in the processor, an extension adapter, programmable logic, a second register file coupled to the programmable logic, and a load/store module. The processor executes a video application that contains an instruction extension not native to the instruction set of the processor. The extension adapter detects the instruction extension in the video application. The programmable logic device is configured to execute the instruction extension. The programmable logic device then executes the instruction extension. The load/store module transfers data between the first register file and the second register file, and transfers data directly between the second register file and a system memory for use by the processor in processing the video application.

Video processing system with reconfigurable instructions

A system and method of mapping heterogeneous objects onto an array of heterogeneous programmable logic resources. The method comprises clustering to identify datapath modules from a netlist. The method further comprises aggregating the datapath modules into higher level modules. The method also comprises clustering random logic into structures.

System and method for efficiently mapping heterogeneous objects onto an array of heterogeneous programmable logic resources

A system and method for adding reconfigurable computational instructions to a reduced instruction set computer. A computer program contains instruction extensions not native to the instruction set of the processor core and is loaded into an instruction memory accessible by the processor core of the computer. The computer program is then detected for containing the instruction extension. The programmable logic device is then configured to execute the instruction extension. The programmable logic device then executes the instruction extension for use by the processor core in processing the computer program.

Reconfigurable instruction set computing

A programmable logic core (PLC) can be integrated into custom ICs such as ASICs and SOCs using a unique design methodology. For example, the methodology can incorporate the PLC into the entire ASIC design process from chip level RTL to final tape-out and resolve issues ranging from RTL guidelines through to sub-micron signal integrity. The post-manufacture programming flow is considered up-front during the ASIC flow and tools ensure successful programming in the field environment for the lifetime of the product. An example PLC architecture for integration into a custom IC includes a Multi Scale Array (MSA) that consists of an array of configurable ALUs and is implemented as a hard macro, an Application Circuit Interface (ACI) that provides signal interface between the MSA and application circuitry and is included in the same hard macro, and a PLC Adapter that initiates and loads the PLC configuration data and interfaces that is implemented as a soft-macro.

Design methodology for merging programmable logic into a custom IC

A programmable logic core (PLC) can be integrated into custom ICS such as ASICs and SOCs. An example PLC for integration into a custom IC includes a Multi Scale Array (MSA) that consists of an array of configurable ALUs, an Application Circuit Interface (ACI) that provides signal interface between the MSA and application circuitry, and a PLC Adapter that initiates and loads the PLC configuration data and interfaces.

Growing community of inventors

San Diego, CA, United States of America

Jeffrey Mark Arnold