Nvidia Corporation

Jeffrey M Smith

Steven E Molnar

Paolo Enrique Sabella

Lincoln G Garlick

Kevin J Kranzusch

Shail Dave

Michael Martin Klock

Lacky V Shah

Samuel Hammond Duncan

James Leroy Deming

Wishwesh Anil Gandhi

Mark Hairgrove

Dennis K Ma

Wei-Je Robert Huang

Vyas Venkataraman

David William Nuechterlein

Jay Gupta

Jonathon Stuart Ramsay Evans

Hemayet Hossain

Satish D Salian

Paul V Puey

Geoffrey Gerfin

Vikramjeet Singh

Paul E Van Der Kouwe

Piyush Patel

Vikram Sethi

Terje Bergstrom

Various embodiments include techniques for accessing extended memory in a parallel processing system via a high-bandwidth path to extended memory residing on a central processing unit. The disclosed extended memory system extends the directly addressable high-bandwidth memory local to a parallel processing system and avoids the performance penalties associated with low-bandwidth system memory. As a result, execution threads that are highly parallelizable and access a large memory space execute with increased performance on a parallel processing system relative to prior approaches.

High bandwidth extended memory in a parallel processing system

A system and method are provided for implementing multi-stage translation of virtual addresses. The method includes the steps of receiving, at a first memory management unit, a memory request including a virtual address in a first address space, translating the virtual address to generate a second virtual address in a second address space, and transmitting a modified memory request including the second virtual address to a second memory management unit. The second memory management unit is configured to translate the second virtual address to generate a physical address in a third address space. The physical address is associated with a location in a memory.

Method and system for implementing multi-stage translation of virtual addresses

An apparatus and method for servicing multiple graphics processing channels are described. In one embodiment, a graphics processing apparatus includes a scheduler configured to direct servicing of a graphics processing channel by issuing an index related to the graphics processing channel. The graphics processing apparatus also includes a processing core connected to the scheduler. The processing core is configured to service the graphics processing channel by: (i) correlating the index with a memory location at which an instance block for the graphics processing channel is stored; and (ii) accessing the instance block stored at the memory location.

Apparatus and method for servicing multiple graphics processing channels

A graphics system adapts a performance level to be sufficient to maintain a performance criterion in an acceptable range. In one embodiment, at least one utilization parameter of the core clock domain and the memory clock domain is monitored. In response to detecting an over-utilization condition, the performance level is increased to maintain the desired minimum number of frames per second. In response to detecting an under-utilization condition, the performance level is decreased to reduce power consumption and increase the lifetime of the graphics system.

Method, apparatus, and system for adaptive performance level management of a graphics system

Software can freeze portions of a pipeline operation in a processor by asserting a predetermined freeze register in the processor. The processor halts operations relating to portions of a common pipeline processing in response to an asserted freeze register. Processor resources that operate downstream from the common pipeline continue to process any scheduled instructions. The processor is prevented from initiating any context switching in which a processor resource is allocated to a different channel. The processor stops supplying any additional data to downstream resources and ensures that the interface to downstream resources is clear of previously sent data. The processor prevents state machines from making additional requests. The processor asserts an acknowledgement indication in response to the freeze assertion when the processing has reached a stable state. Software is allowed to manipulate states and registers within the processor. Clearing the freeze register allows processing to resume.

Indicating acknowledge of stable state of pipeline resource when freeze bit set and context switch inhibited

Overclocking parameters in a graphics system are automatically set. In one embodiment, in response to a user request, overclocking parameters for different sets of overclocking parameters are tested using a graphical stress test to select optimum overclocking parameters.

Method, apparatus, system, and graphical user interface for selecting overclocking parameters of a graphics system

Growing community of inventors

Union City, CA, United States of America

Jeffrey M Smith